IC FLEX 10K FPGA 30K 208-RQFP

EPF10K30RI208-4

Manufacturer Part NumberEPF10K30RI208-4
DescriptionIC FLEX 10K FPGA 30K 208-RQFP
ManufacturerAltera
SeriesFLEX-10K®
EPF10K30RI208-4 datasheet
 


Specifications of EPF10K30RI208-4

Number Of Logic Elements/cells1728Number Of Labs/clbs216
Total Ram Bits12288Number Of I /o147
Number Of Gates69000Voltage - Supply4.5 V ~ 5.5 V
Mounting TypeSurface MountOperating Temperature-40°C ~ 100°C
Package / Case208-RQFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
Other names544-2233  
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Altera Corporation
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices; it provides up to 12 peripheral control signals that
can be allocated as follows:
Up to eight output enable signals
Up to six clock enable signals
Up to two clock signals
Up to two clear signals
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, an LE in a different row can drive a column interconnect,
which causes a row interconnect to drive the peripheral control signal.
The chip-wide reset signal will reset all IOE registers, overriding any other
control signals.
Tables 8
and
9
list the sources for each peripheral control signal, and the
rows that can drive global signals. These tables also show how the output
enable, clock enable, clock, and clear signals share 12 peripheral control
signals.
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