XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 137

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Event 2
Clock Event 4
Clock Event 5
Write Operation
During a write operation, the content of the memory at the location specified by the
address on the ADDR inputs is replaced by the value on the DI pins and is immediately
reflected on the output latches (in WRITE_FIRST mode); when Write Enable (WE) is High.
•
•
•
•
SSR (Synchronous Set/Reset) Operation
During an SSR operation, initialization parameter value SRVAL is loaded into the output
latches of the block RAM. The SSR operation does NOT change the contents of the memory
and is independent of the ADDR and DI inputs.
•
•
Disable Operation
Deasserting the enable signal EN disables any write, read, or SSR operation. The disable
operation does NOT change the contents of the memory or the values of the output latches.
•
•
At time T
inputs of the block RAM.
At time T
the block RAM.
At time T
following the block RAM.
At time T
the block RAM.
At time T
valid (High) at the SSR input of the block RAM.
At time T
outputs of the block RAM.
At time T
EN input of the block RAM.
After clock event 5, the data on the DO outputs of the block RAM is unchanged.
RCCK_EN
RCCK_ADDR
RDCK_DI
RCCK_WE
RCKO_DO
RCCK_SSR
RCKO_DO
before clock event 2, data CCCC becomes valid at the DI inputs of
before clock event 5, the enable signal becomes invalid (Low) at the
after clock event 2, data CCCC becomes valid at the DO outputs of
before clock event 2, write enable becomes valid at the WE
after clock event 4, the SRVAL 0101 becomes valid at the DO
before clock event 4, the synchronous set/reset signal becomes
before clock event 2, address 0F becomes valid at the ADDR
www.xilinx.com
Block RAM Timing Model
137