XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 237

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Output Slew Rate Attributes
Output Drive Strength Attributes
PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF
Differential Termination Attribute
A variety of attribute values provide the option of choosing the desired slew rate for
single-ended I/O output buffers. For LVTTL and LVCMOS output buffers (OBUF, OBUFT,
and IOBUF), the desired slew rate can be specified with the SLEW attribute.
The allowed values for the SLEW attribute are:
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The SLEW attribute uses the following syntax in the UCF file:
By the default, the slew rate for each output buffer is set to SLOW. This is the default used
to minimize the power bus transients when switching non-critical signals.
For LVTTL and LVCMOS output buffers (OBUF, OBUFT, and IOBUF), the desired drive
strength (in mA) can be specified with the DRIVE attribute.
The allowed values for the DRIVE attribute are:
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LVCMOS12 only supports the 2, 4, 6, 8 mA DRIVE settings. LVCMOS15 and LVCMOS18
only support the 2, 4, 6, 8, 12, and 16 mA DRIVE settings.
The DRIVE attribute uses the following syntax in the UCF file:
When using 3-state output (OBUFT) or bidirectional (IOBUF) buffers, the output can have
a weak pull-up resistor, a weak pull-down resistor, or a weak “keeper” circuit. For input
(IBUF) buffers, the input can have either a weak pull-up resistor or a weak pull-down
resistor. This feature can be invoked by adding the following possible constraint values to
the relevant net of the buffers:
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The differential termination (DIFF_TERM) attribute is designed for the Virtex-5 FPGA
supported differential input I/O standards. It is used to turn the built-in, 100Ω, differential
termination on or off.
SLEW = SLOW (Default)
SLEW = FAST
INST <I/O_BUFFER_INSTANTIATION_NAME> SLEW = "<SLEW_VALUE>";
DRIVE = 2
DRIVE = 4
DRIVE = 6
DRIVE = 8
DRIVE = 12 (Default)
DRIVE = 16
DRIVE = 24
INST <I/O_BUFFER_INSTANTIATION_NAME> DRIVE = "<DRIVE_VALUE>";
PULLUP
PULLDOWN
KEEPER
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Virtex-5 FPGA SelectIO Primitives
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