XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 179

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 5-3: Truth Table when SRLOW is Used (Default Condition) (Continued)
Table 5-4: Truth Table when SRHIGH is Used
X-Ref Target - Figure 5-5
SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice
of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) cannot be set
individually for each storage element in a slice.
SR
SR
1
1
0
0
1
1
Figure 5-5: Register/Latch Configuration in a Slice
CLK
DX
CX
SR
BX
CE
AX
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LUT D Output
LUT C Output
LUT B Output
LUT A Output
REV
REV
0
1
0
1
0
1
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR
SR
SR
DFF
CFF
BFF
AFF
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
REV
REV
REV
REV
Q
Q
Q
Q
UG190_5_05_071207
Reset Type
Sync
Async
No Logic Change
DQ
CQ
BQ
AQ
Function
Function
0
0
0
1
0
CLB Overview
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