XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 60

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 2: Clock Management Technology
60
DESKEW_ADJUST Attribute
DFS_FREQUENCY_MODE Attribute
DLL_FREQUENCY_MODE Attribute
DUTY_CYCLE_CORRECTION Attribute
DCM_PERFORMANCE_MODE Attribute
The DESKEW_ADJUST attribute affects the amount of delay in the feedback path. The
possible values are SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS,
0, 1, 2, 3, ..., or 31. The default value is SYSTEM_SYNCHRONOUS.
For most designs, the default value is appropriate. In a source-synchronous design, set this
attribute to SOURCE_SYNCHRONOUS. The remaining values should only be used after
consulting with Xilinx. For more information, consult the
Settingsection.
The DFS_FREQUENCY_MODE attribute specifies the frequency mode of the digital
frequency synthesizer (DFS). The possible values are Low and High. The default value is
Low. The frequency ranges for both frequency modes are specified in the Virtex-5 FPGA
Data Sheet. DFS_FREQUENCY_MODE determines the frequency range of CLKIN, CLKFX,
and CLKFX180.
The DLL_FREQUENCY_MODE attribute specifies either the High or Low frequency
mode of the delay-locked loop (DLL). The default value is Low. The frequency ranges for
both frequency modes are specified in the Virtex-5 FPGA Data Sheet.
The DUTY_CYCLE_CORRECTION attribute controls the duty cycle correction of the 1x
clock outputs: CLK0, CLK90, CLK180, and CLK270. The possible values are TRUE and
FALSE. The default value is TRUE. When set to TRUE, the 1x clock outputs are duty cycle
corrected to be within specified limits. See the Virtex-5 FPGA Data Sheet for details. It is
strongly recommended to always set the DUTY_CYCLE_CORRECTION attribute to
TRUE. Setting this attribute to FALSE does not necessarily produce output clocks with the
same duty cycle as the source clock.
The DCM_PERFORMANCE_MODE attribute allows the choice of optimizing the DCM
either for high frequency and low jitter or for low frequency and a wide phase-shift range.
The attribute values are MAX_SPEED and MAX_RANGE. The default value is
MAX_SPEED. When set to MAX_SPEED, the DCM is optimized to produce high
frequency clocks with low jitter. However, the phase-shift range is smaller than when
MAX_RANGE is selected. When set to MAX_RANGE, the DCM is optimized to produce
low-frequency clocks with a wider phase-shift range. The DCM_PERFORMANCE_MODE
affects the following specifications: DCM input and output frequency range, phase-shift
range, output jitter, DCM_TAP, CLKIN_CLKFB_PHASE, CLKOUT_PHASE, and duty-
cycle precision. The Virtex-5 FPGA Data Sheet specifies these values.
For most cases, the DCM_PERFORMANCE_MODE attribute should be set to
MAX_SPEED (default). Consider changing to MAX_RANGE only in the following
situations:
•
•
The frequency needs to be below the low-frequency limit of the MAX_SPEED setting.
A greater absolute phase-shift range is required.
www.xilinx.com
Source-Synchronous
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010