XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 369

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 8-13
Clock Event 4
The first two bits of the fourth word CD have been sampled into the input side registers of
the ISERDES. On this same edge of CLKDIV, the second word sampled is presented to
Q1–Q4 with one bit shifted to the right. The actual bits from the input stream that appear
at the Q1–Q4 outputs during this cycle are shown in B of
The realigned bits on Q1–Q4 are sampled into the FPGA logic on the CLKDIV domain. The
total latency from when the ISERDES captures the asserted Bitslip input to when the
realigned ISERDES outputs Q1–Q4 are sampled by CLKDIV is two CLKDIV cycles.
Clock Event 5
The third word sampled is presented to Q1–Q4 with three bits shifted to the left. The actual
bits from the input stream that appear at the Q1–Q4 outputs during this cycle are shown in
C of
Figure
C
A
B
8-13.
Q1–Q4 During Clock Event 3
(No Bitslip)
Q1–Q4 During Clock Event 4
(1st Bitslip, Rotate 1 Bit to Right)
Q1–Q4 During Clock Event 5
(2nd Bitslip, Rotate 3 Bits to Left)
Figure 8-13: Bits from Data Input Stream (D) of
www.xilinx.com
Input Serial-to-Parallel Logic Resources (ISERDES)
C D A B C D
C D A B C D
C D A B C D
Figure
A B C D A B
A B C D A B
A B C D A B
8-13.
Figure 8-12
ug190_c8_13_100307
C D
C D
C D
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