XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 152

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 4: Block RAM
152
Case 2: Writing to a Full or Almost Full FIFO
Clock Event 2 and Clock Event 4: Write Operation and Deassertion of Almost
EMPTY Signal
Three read-clock cycles after the fourth data is written into the FIFO, the Almost EMPTY
pin is deasserted to signify that the FIFO is not in the almost EMPTY state.
For the example in
event 2 is with respect to write-clock, while clock event 4 is with respect to read-clock.
Clock event 4 appears three read-clock cycles after clock event 2.
•
•
•
•
If the rising WRCLK edge is close to the rising RDCLK edge, AEMPTY could be deasserted
one RDCLK period later.
Prior to the operations performed in
example, the timing diagram reflects of both standard and FWFT modes.
X-Ref Target - Figure 4-22
WRERR
WRCLK
RDCLK
WREN
AFULL
RDEN
FULL
At time T
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At clock event 4, DO output pins of the FIFO remains at 00 since no read has been
performed. In the case of standard mode, data 00 will never appear at the DO output
pins of the FIFO.
At time T
the AEMPTY pin. In the case of standard mode, AEMPTY deasserts in the same way
as in FWFT mode.
DI
FDCK_DI
FCKO_AEMPTY
Figure
Figure 4-22: Writing to a Full / Almost Full FIFO
1
00
, before clock event 2 (WRCLK), data 03 becomes valid at the DI
www.xilinx.com
4-21, the timing diagram is drawn to reflect FWFT mode. Clock
T
T
, after clock event 4 (RDCLK), almost empty is deasserted at
FCCK_WREN
FDCK_DI
01
Figure
T
FCKO_AFULL
02
4-22, the FIFO is almost completely full. In this
T
FDCK_DI
T
FCKO_FULL
03
T
FCKO_WERR
2
04
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
FCCK_WREN
T
FCKO_WERR
3
05
ug190_4_18_012605
T
FDCK_DI
4
06