XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 92

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: Phase-Locked Loops (PLLs)
General Usage Description
92
PLL Primitives
PLL_BASE Primitive
Figure 3-4
X-Ref Target - Figure 3-4
The PLL_BASE primitive provides access to the most frequently used features of a stand
alone PLL. Clock deskew, frequency synthesis, coarse phase shifting, and duty cycle
programming are available to use with the PLL_BASE. The ports are listed in
Table 3-1: PLL_BASE Ports
Clock Input
Control Inputs
Clock Output
Status and Data Outputs
Description
CLKIN1
CLKFBIN
RST
shows the two Virtex-5 FPGA PLL primitives, PLL_BASE and PLL_ADV.
PLL_BASE
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
LOCKED
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CLKIN, CLKFBIN
RST
CLKOUT0 to CLKOUT5, CLKFBOUT
LOCKED
Figure 3-4: PLL Primitives
Port
CLKIN1
CLKIN2
CLKFBIN
RST
CLKINSEL
DADDR[4:0]
DI[15:0]
DWE
DEN
DCLK
REL
PLL_ADV
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CLKOUTDCM0
CLKOUTDCM1
CLKOUTDCM2
CLKOUTDCM3
CLKOUTDCM4
CLKOUTDCM5
CLKFBDCM
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
LOCKED
DO[15:0]
UG190_c3_04_022709
DRDY
Table
3-1.