XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 312

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
312
Actual SSO Limits versus Nominal SSO Limits
Electrical Basis of SSO Noise
Parasitic Factors Derating Method (PFDM)
Table 6-40: Maximum Number of Simultaneously Switching Outputs per Bank (Continued)
The Virtex-5 FPGA SSO limits are defined for a set of nominal system conditions in
Table
Derating Method (PFDM)
differences between actual and nominal PCB power systems, receiver capacitive loading,
and maximum allowable ground bounce or V
Device SSO
SSO noise can manifest as power supply disturbance, in the form of ground bounce or V
bounce. GND and V
V
V
across power system parasitics by supply current transients. One cause of current
transients is output driver switching events. Numerous output switching events occurring
at the same time lead to bigger current transients, and therefore bigger induced voltages
(ground bounce, V
die, package, and PCB, therefore, parasitics from all three must be considered. The larger
the value of these parasitics, the larger the voltage induced by a current transient (power-
supply disturbance).
V
bounce also affects inputs configured as certain I/O standards because they interpret
incoming signals by comparing them to a threshold referenced to the die ground (as
opposed to I/O standards with input thresholds referenced to a V
voltage disturbance exceeds the instantaneous noise margin for the interface, then a non-
changing input or output can be erroneously interpreted as changing.
SSO noise can also manifest in the form of crosstalk between I/Os in close proximity to one
another. The sparse chevron pinout of Virtex-5 devices reduces crosstalk in the pinout
region to a minimum.
This section describes a method to evaluate whether a design is within the SSO limits when
taking into account the specific electrical characteristics of the user's unique system.
The SSO limits in
These factors fall into three groups of electrical characteristics:
•
CC
CC
CC
Voltage
3.3V
PCB PDS parasitics (nominal 1 nH per via)
rail). The deviation of die supplies from PCB supplies comes from the voltage induced
bounce affects stable high outputs. Ground bounce affects stable low outputs. Ground
rail) with respect to the voltage of the associated PCB supply (PCB GND rail or PCB
6-40. To compute the actual limits for a specific user's system, the
Calculator, automates this process.
GTL
GTL_DCI
GTLP
GTLP_DCI
LVDCI_33 50 Ω
HSLVDCI_33 50 Ω
IOSTANDARD
Table 6-40
CC
CC
bounce, or rail collapse). Relevant transient current paths exist in the
bounce is a deviation of the die supply voltage (die GND rail or die
www.xilinx.com
must be used. The PFDM allows the user to account for
assume nominal values for the parasitic factors of the system.
Limit per 20-pin Bank
CC
12
12
12
12
20
20
bounce. A spreadsheet calculator,
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Limit per 40-pin Bank
REF
voltage). If the die
Parasitic Factors
25
25
25
25
40
40
Full
CC