XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 344

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
OLOGIC Resources
344
X-Ref Target - Figure 7-21
Instantiating Multiple IDELAYCTRLs Without LOC Constraints
Instantiating multiple IDELAYCTRL instances without LOC properties is prohibited. If
this occurs, an error is issued by the implementation tools.
OLOGIC consists of two major blocks, one to configure the output data path and the other
to configure the 3-state control path. These two blocks have a common clock (CLK) but
different enable signals, OCE and TCE. Both have asynchronous and synchronous set and
reset (SR and REV signals) controlled by an independent SRVAL attribute as described in
the
RST_NOLOC
Table 7-1
REFCLK
and
Figure 7-21: Mixed Instantiation of IDELAYCTRL Elements
Table
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rst_1
rst_2
rst_n
7-2.
www.xilinx.com
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all IDELAYCTRL
Replicated for
Instantiated without
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
REFCLK
RST
IDELAYCTRL_noloc
IDELAYCTRL_noloc
IDELAYCTRL_noloc
Instantiated with
LOC Constraint
LOC Constraint
IDELAYCTRL_1
IDELAYCTRL_2
IDELAYCTRL_n
sites
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RDY
RDY
RDY
RDY
RDY
RDY
Auto-generated
by mapper tool
rdy_1
rdy_2
rdy_n
.
.
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RDY_NOLOC
ug190_7_16_041306