XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 42

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VSX50T-3FF1136C

Manufacturer Part Number
XC5VSX50T-3FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VSX50T-3FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Chapter 1: Clock Resources
42
Regional Clock Buffer - BUFR
X-Ref Target - Figure 1-19
The regional clock buffer (BUFR) is another clock buffer available in Virtex-5 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Clock Capable I/O
Not all available BUFIOs are shown.
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
P
P
N
N
P
N
P
N
www.xilinx.com
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
BUFIO
BUFIO
BUFR
BUFR
To Adjacent
Region
To Adjacent
Region
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_19_060706
To Fabric

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