XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 226

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: SelectIO Resources
226
Input Termination to V
Some I/O standards (e.g., HSTL Class I and II) require an input termination voltage of
V
X-Ref Target - Figure 6-10
This is equivalent to having a split termination composed of two resistors. One terminates
to V
V
resistors, i.e., the resistors to V
Both HSTL and SSTL standards need 50 Ω external reference resistors. The DCI input
standards supporting split termination are shown in
Table 6-1: DCI Input Standards Supporting Split Termination
HSTL_I_DCI
HSTL_I_DCI_18
HSTL_II_DCI
HSTL_II_DCI_18
HSTL_II_T_DCI
HSTL_II_T_DCI_18
CCO
CCO
CCO
/2 (see
/2 using split termination. The termination resistance is set by the external reference
, the other to ground. The resistor values are 2R. DCI provides termination to
Figure
Figure 6-10: Input Termination to V
6-10).
CCO
DIFF_HSTL_I_DCI_18
DIFF_HSTL_I_DCI
DIFF_HSTL_II_DCI
DIFF_HSTL_II_DCI_18 SSTL18_II_DCI
www.xilinx.com
/2 (Split Termination)
Z
0
CCO
V
and ground are each twice the reference resistor value.
CCO
R
/2
Virtex-5 FPGA
IOB
V
REF
SSTL2_I_DCI
SSTL2_II_DCI
SSTL18_I_DCI
SSTL2_II_T_DCI
SSTL18_II_T_DCI
Table
CCO
UG190_c6_08_022609
/2 without DCI
6-1.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIFF_SSTL2_I_DCI
DIFF_SSTL2_II_DCI
DIFF_SSTL18_I_DCI
DIFF_SSTL18_II_DCI