XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 157

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

FIFO Applications
X-Ref Target - Figure 4-26
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DI<3:0>
WRCLK
INTCLK
RDCLK
WREN
RDEN
Cascading FIFOs to Increase Depth
DI<3:0>
WREN
RDEN
WRCLK
RDCLK
Case 6: Simultaneous Read and Write for Multirate FIFO
FIFO 1
FWFT
Mode
Simultaneous read and write operations for an asynchronous FIFO is not deterministic
when the FIFO is at the condition to assert a status flag. The FIFO logic resolves the
situation (either assert or not assert the flag), the software simulation model can not reflect
this behavior and mismatch can occur. When using a single clock for RDCLK and WRCLK,
use the FIFO in synchronous mode (EN_SYN=TRUE).
A FIFO larger than a single Virtex-5 FPGA FIFO block can be created by:
•
•
Figure 4-26
the first N–1 FIFOs in FWFT mode and uses external resources to connect them together.
The data latency of this application is the sum of the individual FIFO latencies. The
maximum frequency is limited by the feedback path. The NOR gate is implemented using
CLB logic.
•
•
•
•
Figure 4-26: Example: Cascading Multiple FIFOs by Depth
ALMOSTFULL
Cascading two or more FIFOs to form a deeper FIFO.
Building a wider FIFO by connecting two or more FIFOs in parallel.
N can be 2 or more; if N is 2, the middle FIFOs are not needed.
If WRCLK is faster than RDCLK, then INTCLK = WRCLK
If WRCLK is equal to or slower than RDCLK, then INTCLK = RDCLK
ALMOST_EMPTY threshold is set in the Nth FIFO; ALMOST_FULL threshold is set
in 1st FIFO.
DO<3:0>
EMPTY
FULL
shows a way of cascading N FIFO36s to increase depth. The application sets
DI<3:0>
WREN
RDEN
WRCLK
RDCLK
www.xilinx.com
FIFO 2 ... (N–1)
FWFT
Mode
DO<3:0>
EMPTY
FULL
DI<3:0>
WREN
RDEN
WRCLK
RDCLK
FIFO N
N x 8K x 4 FIFO
DO<3:0>
ALMOST
EMPTY
EMPTY
FULL
FIFO Applications
ug190_4_23_090407
ALMOST
FULL
FULL
DO<3:0>
ALMOST
EMPTY
EMPTY
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