XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 147

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

FIFO Attributes
Table 4-17: FIFO18 and FIFO36 Attributes
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Notes:
1. If FIFO18 is constrained to FIFO18_X#Y#, then RAMB18 can not be constrained to RAMB18_X#Y# since the same location would be
2. If a FIFO18 is constrained to FIFO18_X#Y#, corresponding to the lower RAMB18_X#Y# of the RAMB18 pair, a RAMB18 can be
ALMOST_FULL_OFFSET
ALMOST_EMPTY_OFFSET
FIRST_WORD_FALL_THROUGH
DO_REG
DATA_WIDTH
LOC
EN_SYN
used.
constrained to the upper RAMB18_X#Y# of the pair.
(1, 2)
Attribute Name
Table 4-17
configured by setting the DATA_WIDTH attribute. The
section has examples for setting the attributes.
lists the FIFO18 and FIFO36 attributes. The size of the multirate FIFO can be
13-bit
HEX
13-bit
HEX
Boolean
1-bit
Binary
Integer
String
Boolean
Type
See
See
FALSE,
TRUE
0, 1
4, 9, 18, 36, 72
Valid FIFO18 or
FIFO36 location
FALSE,
TRUE
Table 4-19
Table 4-19
www.xilinx.com
Values
Default
FALSE
1
4
FALSE
Setting determines the difference
between FULL and ALMOSTFULL
conditions. Must be set using
hexadecimal notation.
Setting determines the difference
between EMPTY and ALMOSTEMPTY
conditions. Must be set using
hexadecimal notation.
If TRUE, the first word written into the
empty FIFO appears at the FIFO output
without RDEN asserted.
For multirate (asynchronous) FIFO, must
be set to 1.
For synchronous FIFO, DO_REG must be
set to 0 for flags and data to follow a
standard synchronous FIFO operation.
When DO_REG is set to 1, effectively a
pipeline register is added to the output of
the synchronous FIFO. Data then has a
one clock cycle latency. However, the
clock-to-out timing is improved.
Sets the location of the FIFO18 or FIFO36.
When set to TRUE, ties WRCLK and
RDCLK together.
When set to TRUE, FWFT must be
FALSE.
When set to FALSE, DO_REG must be 1.
FIFO VHDL and Verilog Templates
Notes
FIFO Attributes
147