XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 210

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
Table 5-10: Slice Carry-Chain Timing Parameters
210
Sequential Delays for Slice LUT Configured as Carry Chain
Setup and Hold Times for a Slice LUT Configured as a Carry Chain
Notes:
1. T
T
T
T
T
T
AXCY
OPCYA
BYP
CINA
CINCK
XXCK
/T
/T
/T
/T
= Setup Time (before clock edge), and T
CINB
BXCY
CKCIN
Slice Carry-Chain Timing Model and Parameters
OPCYB
Parameter
/T
/T
CINC
/T
CXCY
Slice Carry-Chain Timing Characteristics
OPCYC
/T
/T
CIND
DXCY
Figure 5-24, page 199
the slice have been omitted for clarity. Only the elements relevant to the timing paths
described in this section are shown.
Slice Carry-Chain Timing Parameters
Table 5-10
Figure 5-24, page
Figure 5-31
Virtex-5 FPGA slice.
X-Ref Target - Figure 5-31
/T
OPCYD
shows the slice carry-chain timing parameters for a majority of the paths in
AX/BX/CX/DX input to
COUT output
CIN input to COUT output
A/B/C/D input to COUT
output
A/B/C/D input to
AMUX/BMUX/CMUX/DMU
X output
CIN Data inputs
illustrates the timing characteristics of a slice carry chain implemented in a
Figure 5-31: Slice Carry-Chain Timing Characteristics
AQ/BQ/CQ/DQ
199.
SR (RESET)
CKXX
illustrates a carry chain in a Virtex-5 FPGA slice. Some elements of
Function
(DATA)
= Hold Time (after clock edge).
(OUT)
CLK
C
www.xilinx.com
IN
1
T
CINCK
T
Propagation delay from the AX/BX/CX/DX
inputs of the slice to the COUT output of the
slice.
Propagation delay from the CIN input of the
slice to the COUT output of the slice.
Propagation delay from the A/B/C/D inputs of
the slice to the COUT output of the slice.
Propagation delay from the A/B/C/D inputs of
the slice to AMUX/BMUX/CMUX/DMUX
output of the slice using XOR (sum).
Time before the CLK that data from the CIN
input of the slice must be stable at the D input of
the slice sequential elements (configured as a
flip-flop).
(1)
CKO
2
3
Description
T
ug190_5_31_050506
SRCK
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
T
CKO