XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 145

• Manufacturer Part Number: XC5VSX50T-3FF1136C
• Description: IC FPGA VIRTEX-5 50K 1136FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Total Ram Bits: 4866048
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Status Flags
Empty Flag
X-Ref Target - Figure 4-20
Table 4-16
FIFO. Synchronous FIFOs do not have a clock cycle latency when asserting or deasserting
flags. Due to the asynchronous nature of the clocks, the simulation model only reflects the
deassertion latency cycles listed.
Table 4-16: Multirate FIFO Flag Assertion and Deassertion Latency
The Empty flag is synchronous with RDCLK, and is asserted when the last entry in the
FIFO is read. When there are no more valid entries in the FIFO queue, the read pointer will
be frozen. The Empty flag is deasserted after three (in standard mode) or four (in FWFT
mode) read clocks after new data is written into the FIFO.
The empty flag is used in the read clock domain. The rising edge of EMPTY is inherently
synchronous with RDCLK. The empty condition can only be terminated by WRCLK,
usually asynchronous to RDCLK. The falling edge of EMPTY must, therefore, artificially
be moved onto the RDCLK time domain. Since the two clocks have an unknown phase
Notes:
1. Latency is with respect to RDCLK and WRCLK.
2. Depending on the offset between read and write clock edges, the Empty and Full flags can deassert
3. Depending on the offset between read and write clock edges, the Almost Empty and Almost Full flags
EMPTY
FULL
ALMOST EMPTY
ALMOST FULL
READ ERROR
WRITE ERROR
DO (Standard)
one cycle later.
can deassert one cycle later.
DO (FWFT)
(2)
EMPTY
RDCLK
(2)
RDEN
Status Flag
shows the number of clock cycles to assert or deassert each flag of a multirate
Figure 4-20: Read Cycle Timing (Standard and FWFT Modes)
(3)
(3)
www.xilinx.com
Previous Data
Standard
W1
0
0
1
1
0
0
Assertion
Write/Read Cycle Latency
FWFT
W2
W1
0
0
1
1
0
0
Standard
W2
W3
3
3
3
3
0
0
Deassertion
FIFO Operations
(1)
ug190_4_17_032506
FWFT
W3
4
3
3
3
0
0
145