XC5VSX50T-3FF1136C Xilinx Inc, XC5VSX50T-3FF1136C Datasheet - Page 364

IC FPGA VIRTEX-5 50K 1136FBGA

XC5VSX50T-3FF1136C

Manufacturer Part Number
XC5VSX50T-3FF1136C
Description
IC FPGA VIRTEX-5 50K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-3FF1136C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
480
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1136-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC5VSX50T-3FF1136C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Chapter 8: Advanced SelectIO Logic Resources
364
Timing Characteristics
Reset Input Timing
Figure 8-8
timing parameter names change for different modes (SDR/DDR). However, the names do
not change when a different bus input width, including when two ISERDES are cascaded
together to form 10 bits. In DDR mode, the data input (D) switches at every CLK edge
(rising and falling).
X-Ref Target - Figure 8-8
Clock Event 1
Clock Event 2
Clock Event 1
As shown in
the pulse must take two different routes to get to ISERDES0 and ISERDES1, there are
different propagation delays for both paths. The difference in propagation delay is
emphasized. The path to ISERDES0 is very long and the path to ISERDES1 is very short,
such that each ISERDES receives the reset pulse in a different CLK cycle. The internal resets
for both CLK and CLKDIV are reset asynchronously when the RST input is asserted.
At time T
and the ISERDES can sample data.
At time T
sampled at the next positive clock edge.
CLK
CE
D
illustrates an ISERDES timing diagram for the input data to the ISERDES. The
Figure
ISCCK_CE
ISDCK_D
1
Figure 8-8: ISERDES Input Data Timing Diagram
T
8-9, the reset pulse is generated on the rising edge of CLKDIV. Because
ISCCK_CE
, before Clock Event 2, the input data pin (D) becomes valid and is
, before Clock Event 1, the clock enable signal becomes valid-High
www.xilinx.com
2
T
ISDCK_D
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_8_08_100307

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