Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 259

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

Application Note
Boost Your System Performance Using The Zilog ESCC
AUTOMATIC OPENING FLAG TRANSMISSION
When Auto Tx Flag (WR7', D0) is enabled, the ESCC
automatically transmits a SDLC opening flag before
transmitting data. This removes:
1. Requirements to reset the mark idle bit (WR10 D3)
2. Waiting for eight bit times to load the opening flag.
TxD Forced High In SDLC With NRZI Encod-
ing When Marking Idle After End Of Frame
When the ESCC is programmed for SDLC mode with NRZI
encoding and mark idle (WR10 D6=0,D5=1,D3=1), TxD is
automatically forced high when the transmitter goes to the
mark idle state at EOF or when Abort is detected. This
6-124
before writing data to the transmitter, or;
RR1
Loaded If
Status FIFO
Is Enabled
CRC/Framing
Error
RX
Overrun
Error
Status
Residue
FIFO
Code
Figure 8. Status FIFO
™
feature is used in combination with the automatic SDLC
opening flag transmission to format the data packets
between
requirement in software intervention.
Status FIFO Enhancement
ESCC SDLC Frame Status FIFO implementation has
been improved to maximize ESCC ability to interface with
a DMA-driven system (Technical Manual, 4.4.3). The
Status FIFO and its relationship with RR1, RR6 and RR7
is shown in Figure 8.
Other special conditions (e.g., Overrun) generates special
receive conditions and lock the Receiver FIFO (Figures 9
and 10).
RR7
successive
Byte Count
frames
RR6
properly
UM010901-0601
without
any