Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 313

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Zilog SCC
SYNCHRONOUS MODES
(SDLC, HDLC, BYSYNC, AND MONOSYNC MODES INCLUDED)
Q. For what are the cyclical redundancy check (CRC)
A. The residue codes provide a secondary method to
Q. Why is the second byte of the CRC incorrect when
A. The second byte of the CRC actually consists of the
Q. How does the SCC send CRC?
A. The SCC can be programmed to automatically send the
Tx Underrun
EOM Latch Bit
The SCC sets the Tx Underrun/EOM latch when the CRC
or Abort is loaded into the shift register for transmission.
This event causes an interrupt (if enabled).
Q. In SDLC, when do you reset the CRC generator
A. The Reset TxCRC Generator command should be is-
Q. How can you make sure that a flag is transmitted
A. Use the external status end of message (EOM) inter-
7-8
residue codes used?
check the reception of the message.
read from the receiving SCC?
last two bits of the first byte or CRC, and the first six
bits of the second byte of CRC.
CRC. First, write the first byte of the message to be
sent. This guarantees the transmitter is full. Then reset
the Transmit Underrun/EOM latch (WR0 10). Write the
rest of the data frame. When the transmit buffer under-
runs, the CRC is sent. The following table describes the
action taken by the SCC for the bit-oriented protocols:
and checker?
sued when the transmitter is enabled and idling
(WR0). This needs to be done only once at initializa-
tion time for SDLC mode.
after CRC?
rupt to start the CRC transmission, then enable the
transmit buffer empty interrupt. When you get the in-
terrupt, it means that the buffer is empty, a flag is load-
ed in the shift register, and you can send the next
packet of information.
0
0
1
Abort/Flag
Bit
X
0
0
Sends CRC +
Flags
Sends Abort +
Flags
Sends Flags
Action Upon
Tx Underrun
Valid Frame
Aborted
Frame
Software
CRC
Comment
Q. If the SCC is idling flags, and a byte of data is
A. Data takes priority over flags and will be loaded in the
Q. Since data is preferred, can this cause a problem?
A. This allows you to append on the end of a message, but
Q. Can you gate data by stretching the receive clock?
A. You can hold the clock until you have valid data. There
Q. How do you synchronize the DPLL in SDLC mode?
A. There are two methods to synchronize the DPLL. Sup-
Q. In SDLC, is the flag and address stripped-off?
A. No, only the flag is stripped. The address will be the
Q. Does IBM
A. No.
Q. Can the SCC include parity in SDLC mode?
A. Yes. It is appended at the end of the character.
Q. How does the SCC operate in transparent mode?
A. The transparentness, as defined by IBM SNA, should
Q. When does the Abort function take effect?
A. The abort takes place immediately by inserting eight
loaded into the transmit buffer, what will be
transmitted?
shift register and transmitted.
it can cause problems with DMA. A character could be
transmitted without an opening flag. To make sure that
a flag has been transmitted, watch for the W/REQ line
to toggle when the flag is loaded into the shift register.
are no maximum specs on the RxC period, and the
edges are used to sample the data. If there are no edg-
es, no data is sampled.
ply at least 16 transitions at the beginning of each
message so the DPLL has time to make adjustments,
or use the DPLL search mode in WR14 to cause the
SCC to synchronize on first transition. The first edge
must be guaranteed to be a cell boundary.
1st character received.
be provided by the software. The SCC does not per-
form any automatic insertion and deletion of link con-
trol nor does it automatically exclude the characters
from the CRC calculation. This also applies to other
high level protocols.
consecutive 1’s.
®
SDLC specify parity?
UM010901-0601