Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 56

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

With only one exception, the /REQ pin directly follows the
state of the transmit buffer (for the ESCC as programmed
by WR7' D5) in this mode. The SCC generates only one
falling edge on /REQ per character requested and the tim-
ing for this is shown in Figure 2-29.
The one exception occurs in synchronous modes at the
end of a CRC transmission. At the end of a CRC transmis-
sion, when the closing flag or sync character is loaded into
the Transmit Shift Register, /REQ is pulsed High for one
UM010901-06
01
(/DTR//REQ)
(/DTR//REQ)
(/W//REQ)
(/W//REQ)
AD7-AD0
D7-D0
PCLK
/REQ
/REQ
/WR
PCLK
/REQ
/REQ
/DS
/AS
WR8
Transmit Data
Figure 2-29. Z80X30 Transmit Request Release
Figure 2-30. Z85X30 Transmit Request Release
Transmit Data
PCLK cycle. The DMA uses this falling edge on /REQ to
write the first character of the next frame to the SCC. In the
case of the Z80X30, /REQ goes High in response to the
falling edge of DS, but only if the appropriate channel
transmit buffer in the SCC is accessed. This is shown in
Figure 2-25. In the case of the Z85X30, /REQ goes High in
response to the falling edge of /WR, but only when the ap-
propriate channel transmit buffer in the SCC is accessed.
This is shown in Figure 2-30.
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2-37
2