Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 301

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

Application Note
Interfacing the ISCC™ to the 68000 and 8086
APPLICATIONS EXAMPLES
The following application examples explain and illustrate
the methods of interfacing the ISCC to a Motorola 68000
and an Intel 8086.
68000 Interface to the ISCC
Figure A-3 shows a connection of the ISCC to a 68000
microprocessor. The 68000 data bus connects directly, or
through bus transceivers, to the ISCC address/data bus.
R/W and RESET also directly connect. In this example, the
ISCC is on the lower half of the bus; DS of the ISCC
connects to LDS of the 68000. The processor address
lines decode to produce a chip enable for the ISCC. In
addition, processor addresses A1 and A2 connect to
A0/SCC/DMA and A1/A/B, respectively, through a tri-state
driver.
The driver is normally ON (enabled) but turns OFF by
BGACK to grant the bus to ISCC for DMA transfers. This
is done since the A0/SCC/DMA and A1/A/B pins become
outputs during DMA transfers and should not drive the
system address bus. RD and WR tie high through
independent pull-ups. They are not used in this application
but become active outputs during DMA transfers and are
not tied directly to V
Although not shown in Table A-5, the A0/SCC/DMA and
A1/A/B pins may be decoded during DMA transfers to
identify the active DMA channel.
External logic can use this information to abort a DMA in
progress.
For normal slave device bus interaction, a DTACK is
generated. WAIT/RDY is programed for ready operation
and INTACK programs for the status type. WAIT/RDY
generates a DTACK for normal data transfers and interrupt
responses. Additional logic may be required when other
interrupt sources are present.
During DMA transfers, the ISCC becomes bus master.
Becoming bus master is done through the BUSREQ
output and BUSACK input signals of the ISCC. They
connect to an external bus arbitration circuit. This circuit
6-6
A1/A/B
1
1
0
0
Table 43. DMA A/B Channel Decode
A0/SCC/DMA DMA Channel
CC
.
1
0
1
0
Receiver Channel A
Transmitter Channel A
Receiver Channel B
Transmitter Channel B
performs bus arbitration for multiple bus master requests
and generates bus grant acknowledge (BGACK) which
controls certain bus drive signal sources.
When the ISCC becomes the bus master, a 32-bit address
generation by the DMA section is output on the ISCC
address/data bus. The lower 16 bits of this address store
in an external latch by AS (Address Strobe). Also, the
upper 16 bits of this address store in an external latch by
UAS (Upper Address Strobe). With BGACK low (active)
and with the processor address lines tri-stated, the latch
outputs drive the system address bus.
AS is pulled high by an external resistor. This pull-up
insures an inactive AS (at a logic high level) when the
ISCC is not driving this signal. Therefore, on power up or
after a RESET, AS is inactive and programs the non-
multiplexed bus mode on BCR write.
In this application, the outputs of the address latches are
connected to the address bus so that A1 through A23 of
the ISCC drives the system address bus (the ISCC
provides a total of 32 address lines). A0 from the address
latch is diverted to logic which generates UDS and LDS
bus signals from the ISCC data strobe (DS). UDS is
generated when A0 is low and LDS is generated when A0
is high. The lower and upper data strobes are applied to
the system bus through tri-state drivers which are enabled
only when BGACK is active. Bus direction is now
controlled by the ISCC R/W signal which is now an output.
For initialization, the BCR write (the first write to the ISCC
after RESET) is done with A2 = 0 (A1/A/B ISCC input at
logic low). This selects the ready option of the WAIT/RDY
signal to conform to the 68000 bus style. The AS signal
programming of the non-multiplexed bus has already been
discussed. The BCR is written with C0H to enable byte
swapping. It also selects the sense of byte swapping with
respect to A0 appropriate to this bus style and selects the
STATUS type of interrupt acknowledge.
8086 Interface with the ISCC
Figure A-4 shows the connection of the ISCC to an 8086
microprocessor and companion clock state generator. In
this application, the ISCC connects for multiplexed
address access to the internal ISCC registers. AD15
through AD0 of the 8086 connect directly, or through a bus
transceiver, to the corresponding AD15 through AD0
address/data ISCC bus pins. RD and WR are directly
compatible and tie together to form the read and write bus
signals.
UM010901-0601