Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 35

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
2.4.2 Polling
This is the simplest mode to implement. The software must
poll the SCC to determine when data is to be input or out-
put from the SCC. In this mode, MIE (WR9, bit 3), and
Wait/DMA Request Enable (WR1, bit 7) are both reset to 0
to disable any interrupt or DMA requests. The software
must then poll RR0 to determine the status of the receive
buffer, transmit buffer and external status.
During a polling sequence, the status of Read Register 0
is examined in each channel. This register indicates
whether or not a receive or transmit data transfer is need-
ed and whether or not any special conditions are present,
e.g., errors.
This method of I/O transfer avoids interrupts and, conse-
quently, all interrupt functions should be disabled. With no
interrupts enabled, this mode of operation must initiate a
read cycle of Read Register 0 to detect an incoming char-
acter before jumping to a data handler routine.
2-16
Receive Character Available
Receive Overrun
Framing Error
End of Frame (SDLC)
Parity Error (If enabled)
Transmit Buffer Empty
Zero Count
DCD
SYNC/HUNT
CTS
Tx Underrun/EOM
Break/Abort
Figure 2-9. ESCC Interrupt Sources
INT on first Rx Character
or Special Condition
External/Status
2.4.3 Interrupts
Each of the SCC’s two channels contain three sources of
interrupts, making a total of six interrupt sources. These
three sources of interrupts are: 1) Receiver, 2) Transmit-
ter, and 3) External/Status conditions. In addition, there
are several conditions that may cause these interrupts.
Figure 2-9 shows the different conditions for each interrupt
source and each is enabled under program control. Chan-
nel A has a higher priority than Channel B with Receive,
Transmit, and External/Status Interrupts prioritized, re-
spectively, within each channel as shown in Table 2-8. The
SCC internally updates the interrupt status on every PCLK
cycle in the Z85X30 and on /AS in the Z80X30.
Transmitter
Receiver
Interrupt
Interrupt
Interrupt
Sources
Sources
Receive Channel A
Transmit Channel A
External/Status Channel A
Receive Channel B
Transmit Channel B
External/Status Channel B
Source
INT on all Rx Character
or Special Condition
Rx Interrupt on Special
Condition Only
Table 2-8. Interrupt Source Priority
Interrupt
SCC
UM010901-0601
Highest
Lowest