Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 4

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
SCC™/ESCC™ User’s Manual
Table of Contents
Chapter 3. SCC/ESCC Ancillary Support Circuitry
Chapter 4. Data Communication Modes
Chapter 5. Register Descriptions
3.1
3.2
3.3
3.4
3.5
3.6
4.1
4.2
4.3
4.4
5.1
5.2
5.3
Introduction .................................................................................................................................... 3-1
Baud Rate Generator ..................................................................................................................... 3-1
3.4.1
3.4.2
3.4.3
3.4.4
Introduction .................................................................................................................................... 4-1
4.1.1
4.1.2
Asynchronous Mode ...................................................................................................................... 4-3
4.2.1
4.2.2
4.2.3
4.3.1
4.3.2
4.3.3
4.4.1
4.4.2
4.4.3
4.4.4
Introduction .................................................................................................................................... 5-1
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.2.10 Write Register 7 Prime (85C30 only) .............................................................................. 5-13
5.2.11 Write Register 8 (Transmit Buffer) .................................................................................. 5-13
5.2.12 Write Register 9 (Master Interrupt Control) .................................................................... 5-14
5.2.13 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) ........................... 5-15
5.2.14 Write Register 11 (Clock Mode Control) ......................................................................... 5-17
5.2.15 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) ....................... 5-18
5.2.16 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) ....................... 5-19
5.2.17 Write Register 14 (Miscellaneous Control Bits) .............................................................. 5-19
5.2.18 Write Register 15 (External/Status Interrupt Control) ..................................................... 5-20
Read Registers ............................................................................................................................ 5-21
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Data Encoding/Decoding ............................................................................................................... 3-4
DPLL Digital Phase-Locked Loop .................................................................................................. 3-7
Byte-Oriented Synchronous Mode ................................................................................................. 4-8
Bit-Oriented Synchronous (SDLC/HDLC) Mode .......................................................................... 4-18
Write Registers .............................................................................................................................. 5-2
Clock Selection ........................................................................................................................... 3-11
Crystal Oscillator ......................................................................................................................... 3-14
DPLL Operation in the NRZI Mode .................................................................................. 3-8
DPLL Operation in the FM Modes .................................................................................... 3-9
DPLL Operation in the Manchester Mode ...................................................................... 3-10
Transmit Clock Counter (ESCC only) ............................................................................. 3-10
Transmit Data Path Description ....................................................................................... 4-1
Asynchronous Transmit ................................................................................................... 4-4
Asynchronous Receive .................................................................................................... 4-6
Asynchronous Initialization ............................................................................................... 4-7
Byte-Oriented Synchronous Transmit .............................................................................. 4-8
Byte-Oriented Synchronous Receive ............................................................................. 4-10
Transmitter/Receiver Synchronization ........................................................................... 4-17
SDLC Transmit ............................................................................................................... 4-19
SDLC Receive ................................................................................................................ 4-22
SDLC Frame Status FIFO .............................................................................................. 4-27
SDLC Loop Mode ........................................................................................................... 4-30
Write Register 0 (Command Register) ............................................................................. 5-2
Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) .......... 5-4
Write Register 2 (Interrupt Vector) ................................................................................... 5-7
Write Register 3 (Receive Parameters and Control) ........................................................ 5-7
Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) .................. 5-8
Write Register 5 (Transmit Parameters and Controls) ..................................................... 5-9
Write Register 6 (Sync Characters or SDLC Address Field) .......................................... 5-10
Write Register 7 (Sync Character or SDLC Flag) ........................................................... 5-11
Write Register 7 Prime (ESCC only) .............................................................................. 5-12
Read Register 0 (Transmit/Receive Buffer Status and External Status) ........................ 5-21
Read Register 1 ............................................................................................................. 5-23
Read Register 2 ............................................................................................................. 5-24
Read Register 3 ............................................................................................................. 5-25
Read Register 4 (ESCC and 85C30 Only) ..................................................................... 5-25
Read Register 5 (ESCC and 85C30 Only) ..................................................................... 5-25
Receive Data Path Description ....................................................................................... 4-2
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