Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 93

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
0s be transmitted, the Send Break bit (D4) in WR5 is set
to 1. The transmitter is now idling but is still placed in the
transmitter to receiver synchronization mode. This is ac-
complished by setting the Loop Mode bit (D1) in WR10
and then enabling the transmitter by setting bit D3 of
WR5 to 1. At this point, the processor should set the Go
Active on Poll bit (D4) in WR10. The final step is to force
4.4 BIT-ORIENTED SYNCHRONOUS (SDLC/HDLC) MODE
Synchronous Data Link Control mode (SDLC) uses syn-
chronization characters similar to Bisync and Monosync
modes (such as flags and pad characters). It is a bit-orient-
ed protocol instead of a byte-oriented protocol. High level
Data Link Control (HDLC) is defined as CCITT, also EIAJ
and other standards; SDLC is one of the implementations
made by IBM
zero insertion to make all data transparent from SYNC
characters. All references to SDLC in this manual apply to
both SDLC and HDLC.
Frames of information are enclosed by a unique bit pattern
called a flag. The flag character has a bit pattern of
“01111110” (7E Hex). This sequence of six consecutive
ones is unique because all data between the opening and
closing flags is prohibited from having more than five con-
secutive 1s. The transmitter guarantees this by watching
the transmit data stream and inserting a 0 after five con-
secutive 1s, regardless of character boundaries. In turn,
the receiver searches the receive data stream for five con-
secutive 1s and deletes the next bit if it is a 0. Since the
SDLC mode does not use characters of defined length, but
rather works on a bit-by-bit basis, the 01111110 flag can
be recognized at any time. Inserted and removed 0s are
not included in the CRC calculation. Since the transmis-
sion of the flag character is excluded from the zero inser-
tion logic, its transmission is guaranteed to be seen as a
flag by the receiver. The zero insertion and deletion is
completely transparent to the user.
Because of the zero insertion/deletion, actual bit length on
the transmission line may be longer than the number of
bits sent.
4-18
®
. The SDLC protocol uses the technique of
Beginning Flag
01111110
8 Bits
Address
8 Bits
Figure 4-11. SDLC Message Format
Control
8 Bits
Frame
Any Number
Information
the receiver to search for sync characters. If the receiver
is currently disabled, the receiver enters Hunt mode
when it is enabled, by setting bit D0 of WR3 to 1. If the
receiver is already enabled, it is placed in Hunt mode by
setting bit D4 of WR3 to 1. Once the receiver leaves
Hunt mode, the transmitter is activated on the following
character boundary.
The basic format for SDLC is a frame (Figure 4-11). A
Frame is marked at the beginning and end by a unique flag
pattern.
information, and frame check fields. There are many
different implementations of the SDLC protocol and many
do not use all of the fields. The SCC provides many
features to control how each of the fields is received and
transmitted.
The two flags that delineate the SDLC frame serve as ref-
erence points when positioning the address and control
fields, and they initiate the transmission error check. The
ending flag indicates to the receiving station that the 16-
bits just received constitute the frame check (CRC; also re-
ferred to as FCS or Frame Check Sequence). The ending
flag can be followed by another frame, another flag, or an
idle. This means that when two frames follow one another,
the intervening flag may simultaneously be the ending flag
of the first frame and the beginning flag of the next frame.
This case is usually referred to as “Back-to-Back Frames”.
The SCC’s SDLC address field is eight bits long and is
used to designate which receiving stations accept a trans-
mitted message. The 8-bit address allows up to 254
(00000001 through 11111110) stations to be addressed
uniquely or a global address (11111111) is used to broad-
cast the message to all stations. Address 0 (00000000) is
usually used as a Test packet address.
The control field of a SDLC frame is typically 8 bits, but can
be any length. The control field is transparent to the SCC
Of Bits
The
16 Bits
Frame
Check
flags
enclose
Ending Flag
01111110
8 Bits
an
address,
UM010901-0601
control,