Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 50

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-06
01
2.4.9 External/Status Interrupts
Each channel has six external/status interrupt conditions:
BRG Zero Count, Data Carrier Detect, Sync/Hunt, Clear to
Send, Tx Underrun/EOM, and Break/Abort. The master
enable for external/status interrupts is D0 of WR1, and the
individual enable bits are in WR15. Individual enable bits
control whether or not a latch is present in the path from
the source of the interrupt to the corresponding status bit
in RR0. If the individual enable is set to 0, then RR0 re-
flects the current unlatched status, and if the individual en-
able is set to 1, then RR0 reflects the latched status.
The latches for the external/status interrupts are not inde-
pendent. Rather, they all close at the same time as a result
of a state change in one of the sources of enabled exter-
nal/status interrupts. This is shown schematically in
Figure 2-23.
External/St
External/St
Condition
Condition
IE = 1
IE = 0
with
with
Figure 2-23. RR0 External/Status Interrupt Operation
Latch
The External/Status IP is set by the closing of the latches
and remains set as long as they are closed. In order to de-
termine which condition(s) require service when an exter-
nal/status interrupt is received, the processor should keep
an image of RR0 in memory and update this image each
time it executes the external/status service routine.
Thus, a read of RR0 returns the current status for any bits
whose individual enable is 0, and either the current state
or the latched state of the remainder of the bits. To
guarantee the current status, the processor should issue a
Reset External/Status interrupts command in WR0 to open
the latches. The External/Status IP is set by the closing of
the latches and remains set as long as they are closed. If
the master enable for the External/Status interrupts is not
set, the IP is never set, even though the latches may be
present in the signal paths and working as described.
Detecto
Change
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
To IP
To RR0
2-31
2