Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 76

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
4.1 INTRODUCTION
The SCC provides two independent, full-duplex channels
programmable for use in any common asynchronous or
synchronous data communication protocol. The data com-
munication protocols handled by the SCC are:
Asynchronous mode:
Asynchronous (x16, x32, or x64 clock
Isochronous (x1 clock)
Character-Oriented mode:
Monosynchronous
Bisynchronous
External Synchronous
Bit-Oriented mode
SDLC/HDLC
SDLC/HDLC Loop
From Receiver
SYNC
5-Bit Delay
CRC-SDLC
CRC-Gen
WR7
Insert
Zero
Register
20-Bit TX Shift Register
SYNC
Internal Data Bus
Figure 4-1. Transmit Data Path
WR6
Register
ASYNC
SYNC
SDLC
MUX & 2-Bit
WR8
Transmit
Delay
U
C
D
Transmit Clock
4.1.1 Transmit Data Path Description
A diagram of the transmit data path is shown in Figure 4-1.
The transmitter has a Transmit Data buffer (a 4-byte deep
FIFO on the ESCC, a one byte deep buffer on the
NMOS/CMOS version) which is addressed through WR8.
It is not necessary to enable the transmit buffer. It is
available in all modes of operation. The Transmit Shift
register is loaded from either WR6, WR7, or the Transmit
Data buffer. In Synchronous modes, WR6 and WR7 are
programmed with the sync characters. In Monosync mode,
an 8-bit or 6-bit sync character is used (WR6), whereas a
16-bit sync character is used in the Bisynchronous mode
(WR6 and WR7). In bit-oriented Synchronous modes, the
SDLC flag character (7E hex) is programmed in WR7 and
is loaded into the Transmit Shift Register at the beginning
and end of each message.
SER
ATA
HAPTER
TX Buffer (1-Byte; NMOS/CMOS)
TX FIFO (4 Byte; ESCC)
’
S
C
M
OMMUNICATION
ANUAL
Internal TxD
Final TX
Encode
NRZI
MUX
4
To Other Channel
TxD
M
ODES
4-1
4