Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 7

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
Figure 2-27.
Figure 2-28.
Figure 2-29.
Figure 2-30.
Figure 2-31.
Figure 2-32.
Figure 2-33.
Figure 2-34.
Figure 2-35.
Figure 2-36.
Chapter 3
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 3-6.
Figure 3-7.
Figure 3-8.
Figure 3-9.
Figure 3-10.
Figure 3-11.
Figure 3-12.
Figure 3-13.
Chapter 4
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 4-7.
Figure 4-8.
Figure 4-9.
Figure 4-10.
Figure 4-11.
Figure 4-12.
Figure 4-13.
Figure 4-14.
Figure 4-15.
Figure 4-16.
Chapter 5
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Wait On Receive Timing ..................................................................................................................... 2-35
Transmit Request Assertion ............................................................................................................... 2-36
Z80X30 Transmit Request Release ................................................................................................... 2-37
Z85X30 Transmit Request Release ................................................................................................... 2-37
/DTR//REQ Deassertion Timing ......................................................................................................... 2-38
DMA Receive Request Assertion ....................................................................................................... 2-39
Z80X30 Receive Request Release .................................................................................................... 2-40
Z85X30 Receive Request Release .................................................................................................... 2-40
Local Loopback .................................................................................................................................. 2-41
Auto Echo ........................................................................................................................................... 2-41
Baud Rate Generator ........................................................................................................................... 3-1
Baud Rate Generator Start Up ............................................................................................................. 3-2
Data Encoding Methods ....................................................................................................................... 3-4
Manchester Encoding Circuit ................................................................................................................ 3-6
Digital Phase-Locked Loop ................................................................................................................... 3-7
DPLL in NRZI Mode ............................................................................................................................. 3-8
DPLL Operating Example (NRZI Mode) ............................................................................................... 3-9
DPLL Operation in the FM Mode .......................................................................................................... 3-9
DPLL Transmit Clock Counter Output (ESCC only) ........................................................................... 3-11
Clock Multiplexer ................................................................................................................................ 3-12
Async Clock Setup Using an External Crystal .................................................................................... 3-13
Clock Source Selection ...................................................................................................................... 3-13
Synchronous Transmission, 1x Clock Rate, FM Data Encoding, using DPLL ................................... 3-14
Transmit Data Path ............................................................................................................................... 4-1
Receive Data Path ................................................................................................................................ 4-2
Asynchronous Message Format ........................................................................................................... 4-3
Monosync Data Character Format ....................................................................................................... 4-8
Sync Character Programming ............................................................................................................ 4-11
/SYNC as an Input .............................................................................................................................. 4-11
/SYNC as an Output ........................................................................................................................... 4-12
Changing Character Length ............................................................................................................... 4-13
Receive CRC Data Path ..................................................................................................................... 4-14
Transmitter to Receiver Synchronization ............................................................................................ 4-17
SDLC Message Format ...................................................................................................................... 4-18
/SYNC as an Output ........................................................................................................................... 4-23
Changing Character Length ............................................................................................................... 4-24
Residue Code 101 Interpretation ........................................................................................................ 4-25
SDLC Frame Status FIFO (N/A on NMOS) ........................................................................................ 4-28
SDLC Byte Counting Detail ................................................................................................................ 4-29
Write Register 0 in the Z85X30 ............................................................................................................ 5-3
Write Register 0 in the Z80X30 ............................................................................................................ 5-3
Write Register 1 .................................................................................................................................... 5-4
Write Register 2 .................................................................................................................................... 5-7
Write Register 3 .................................................................................................................................... 5-7
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