Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 31

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.3 Z85X30 INTERFACE TIMING (Continued)
Between the time /INTACK is first sampled Low and the
time /RD falls, the internal and external IEI/IEO daisy chain
settles (AC parameter #38 TdIAI(RD) Note 5). A system
with no external daisy chain must provide the time speci-
fied in AC Spec #38 to settle the interrupt daisy chain pri-
ority internal to the SCC. Systems using the external
IEI/IEO daisy chain should refer to Note 5 referenced in the
Z85X30 Read/Write and Interrupt Acknowledge Timing for
the time required to settle the daisy chain.
Note: /INTACK is sampled on the rising edge of PCLK. If it
does not meet the setup time to the first rising edge of PCLK
of the interrupt acknowledge cycle, it is latched on the next
rising edge of PCLK. Therefore, if /INTACK is asynchronous
to PCLK, it may be necessary to add a PCLK cycle to the
calculation for /INTACK to /RD delay time.
If there is an interrupt pending in the Z85X30, and IEI is
High when /RD falls, the interrupt acknowledge cycle was
2.3.4 Z85X30 Register Access
The registers in the Z85X30 are accessed in a two step
process, using a Register Pointer to perform the address-
ing. To access a particular register, the pointer bits are set
by writing to WR0. The pointer bits may be written in either
channel because only one set exists in the Z85X30. After
the pointer bits are set, the next read or write cycle of the
Z85X30 having D//C Low will access the desired register.
At the conclusion of this read or write cycle the pointer bits
are reset to 0s, so that the next control write is to the point-
ers in WR0.
A read to RR8 (the receive data FIFO) or a write to WR8
(the transmit data FIFO) is either done in this fashion or by
accessing the Z85X30 having D//C pin High. A read or
write with D//C High accesses the data registers directly,
and independently of the state of the pointer bits. This al-
lows single-cycle access to the data registers and does not
disturb the pointer bits.
2-12
intended for the Z85X30. In this case, the Z85X30 sets the
appropriate Interrupt-Under-Service latch, and places an
interrupt vector on D7-D0.
If the falling edge of /RD sets an IUS bit in the Z85X30, the
/INT pin goes inactive in response to the falling edge. Note
that there should be only one /RD per acknowledge cycle.
Note 1: The IP bits in the Z85X30 are updated by PCLK.
However, when the register pointer is pointing to RR2 and
RR3, the IP bits are prevented from changing. This pre-
vents data changing during a read, but will delay interrupt
requests if the pointers are left pointing at these registers.
Note 2: The SCC should only receive one INTACK signal
per acknowledge cycle. Therefore, if the CPU generates
more than one (as is common for the 80X86 family), an ex-
ternal circuit should be used to convert this into a single
pulse or does not use Interrupt Acknowledge.
The fact that the pointer bits are reset to 0, unless explicitly
set otherwise, means that WR0 and RR0 may also be ac-
cessed in a single cycle. That is, it is not necessary to write
the pointer bits with 0 before accessing WR0 or RR0.
There are three pointer bits in WR0, and these allow ac-
cess to the registers with addresses 7 through 0. Note that
a command may be written to WR0 at the same time that
the pointer bits are written. To access the registers with ad-
dresses 15 through 8, the Point High command must ac-
company the pointer bits. This precludes concurrently is-
suing a command when pointing to these registers.
The register map for the Z85X30 is shown in Table 2-5. If,
for some reason, the state of the pointer bits is unknown
they may be reset to 0 by performing a read cycle with the
D//C pin held Low. Once the pointer bits have been set, the
desired channel is selected by the state of the A//B pin dur-
ing the actual read or write of the desired register.
UM010901-0601