MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 109

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

3
3-24
NOTES:
2. Where r is rounding precision, S or D.
3. A list of any combination of the eight floating-point data registers, with individual register names separated by a slash
4. A list of any combination of the three floating-point system control registers (FPCR, FPSR, and FPIAR) with individual
5. where d is direction, L or R.
1. Specifies either the instruction (IC), data (DC), or IC/DC caches.
Opcode
TRAPcc
TRAPV
SWAP
SBCD
STOP
SUBA
SUBQ
SUBX
TRAP
UNPK
UNLK
(/J; and/or contiguous blocks of registers specified by the
register names separated by a slash (/).
SUBI
SUB
TAS
RTD
RTR
RTS
TST
RTE
Scc
else Os 0 Destination
else TRAP
Destination- Source ~ Destination
Destination
Destination
SSP 2 I SSP; Format/Offset ~ (SSP);
SSP-4 B SSP; PC 0 (SSP); SSP-2 1 SSP;
SR i) (SSP); Vector Address J PC
If cc then TRAP
An i SP; (SP) I~ An; SP+4 I) SP
If supervisor state
else TRAP
(SP) j CCR; SP+2 0 SP;
<SP/0 PC, SP+4 ~ SP
(SP) B PC; SP÷4 ~ SP
Destination10 S o u r c e l 0 - X I) Destination
If Condition True
If supervisor state
Destination-Source j Destination
Destination-Source
If V then TRAP
Destination Tested J Condition Codes
Source (Packed BCD)+ adjustment J Destination (Unpacked BCD)
(SP) I) PC; S P + 4 + d 0 SP
Register [31:16] ~0 Register [15:0]
Destination Tested I) Condition Codes; 1 I) bit 7 of Destination
then Immediate Data J SR; STOP
the (SP) I) SR; SP+20 SP; (SP) I) PC;
then ls 0 Destination
SP + 4 i SP;
restore state and deallocate stack according to (SP)
Table 3-14. Instruction Set Summary (Sheet 5 of 5)
Immediate Data 0 Destination
Immediate Data ~ Destination
X ~ Destination
MC68030 USER'S MANUAL
Operation
first
and
last
register
STOP #<data)
SUBA (ea),An
SUBI #(data),(ea)
SUBQ #(data),(ea)
SUBX Dx,Dy
S U B X - ( A x ) ,
SWAP Dn
TAS (ea)
TRAP #<vector)
TRAPcc
TRAPcc.W #<data}
TRAPcc.L #<data}
TRAPV
TST (ea)
UNPACK - (Ax),- (Ay),#(adjustment)
UNPACK Dx,Dy,#(adjustment)
RTD #(disp]acement)
RTE
RTR
RTS
SBCD Dx,Dy
SBCD
Scc (ea)
SUB (ea),Dn
SUB Dn,(ea)
UNLK An
names separated
-(Ax),
Syntax
(Ay)
(Ay)
by a
dash
MOTOROLA
(-).