MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 468

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

11.2.5.1 INSTRUCTION FETCH PENDING BUFFER. The instruction prefetch mech-
11.2.5.2 WRITE PENDING BUFFER. The MC68030 incorporates a single write
11.2.5.3 MICRO BUS CONTROLLER. The micro bus controller performs the bus
MOTOROLA
the microsequencer from overwriting this buffer.
When prefetching instructions from external memory, the micro bus con-
troller utilizes long-word read cycles. The processor reads two words, which
codes. The microsequencer may also request a bus cycle that the bus con-
troller cannot perform immediately. In this case, the bus cycle is queued and
the bus controller runs the cycle when the current cycle is complete.
The bus controller consists of the micro bus controller, the instruction fetch
pending buffer, and the write pending buffer. These three resources carry
out all writes and reads that miss in the on-chip caches.
anism includes a single long-word instruction fetch pending buffer. Interlocks
are provided to prevent this buffer from being overwritten by an instruction
cycles issued to the bus controller by the rest of the processor. It implements
any dynamic bus sizing required and also controls burst operations.
into the cache holding register (and the instruction cache if it is enabled and
cache miss. From a 32-bit memory, the MC68030 reads both the even and
odd words associated with the long-word base address in one bus cycle.
odd word. Both the even and odd word are loaded into the cache holding
prefetch request before a previously requested prefetch is completed.
pending buffer, allowing the microsequencer to continue execution after the
request for a write cycle proceeds to the bus controller. Interlocks prevent
may load two instructions at once or two words of a multi-word instruction
not frozen). A special case occurs when prefetch, that. corresponds to an
instruction word at an odd-word boundary, is not found in the cache holding
register (e.g., due to a branch to an odd-word location) with an instruction
From an 8- or 16-bit memory, the processor reads the even word before the
register (and the instruction cache if it is enabled and not frozen).
MC68030 USER'S MANUAL
11-5
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