MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 276

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.1.4 Instruction Trap Exception
MOTOROLA
8.1.5 Illegal Instruction and Unimplemented Instruction Exceptions
ternally, enters the supervisor privilege level, and clears the trace bits. If
tracing is enabled for the instruction that caused the trap, a trace exception
trace corresponds to the trap instruction; the trap handler routine is not
traced. The processor generates a vector number according to the instruction
system calls in user programs. The TRAPcc, TRAPV, cpTRAPcc, CHK, and
The DIVS and DIVU instructions force exceptions if a division operation is
attempted with a divisor of zero.
When a trap exception occurs, the processor copies the status register in-
of the program counter is the logical address of the instruction following the
Certain instructions are used to explicitly cause trap exceptions. The TRAP
#n instruction always forces an exception and is useful for implementing
CHK2 instructions force exceptions if the user program detects an error, which
may be an arithmetic overflow or a subscript value that is out of bounds.
is taken after the RTE instruction from the trap handler is executed, and the
being executed; for the TRAP #n instruction, the vector number is 32 plus
n. The stack frame saves the trap vector offset, the program counter, and the
internal copy of the status register on the supervisor stack. The saved value
instruction that caused the trap. For all instruction traps other than TRAP #n,
a pointer to the instruction that caused the trap is also saved. Instruction
execution resumes at the address in the exception vector after the required
instruction prefetches.
An illegal instruction is an instruction that contains any bit pattern in its first
word t h a t does not correspond to the bit pattern of the first word of a valid
specification field in the first extension word. An illegal instruction exception
corresponds to vector number 4 and occurs when the processor attempts to
execute an illegal instruction.
MC68030 instruction or is a MOVEC instruction with an undefined register
MC68030 USER'S MANUAL
8-9
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