MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 221

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-60
tains AS, DS, R/W, A0-A31, FC0-FC2, SIZ0-SlZl in their current state through-
then be negated, and the MC68030 latches the data for the fourth cycle and
The following conditions can abort a burst fill:
The processing of a bus error during a burst fill operation is described in
the processor with BR, a burst operation is a single cycle since AS remains
TRATION
the read or write cycles of any read-modify-write operation:
The MC68030 allows burst filling only from 32-bit ports that terminate bus
cycles with STERM and respond to CBREQ by asserting CBACK. When the
out the burst operation. The processor continues to accept data on every
clock during which STERM is asserted until the burst is complete or an
abnormal termination occurs:
CBACK indicates that the addressed device can respond to a cache burst
request by supplying one more long word of data in the burst mode. It can
initiated if both of these signals are asserted for a synchronous cycle. If the
is negated after STERM is asserted for the third cycle, indicating that the
MC68030 only requests one more long word (the fourth cycle). CBACK can
completes the cache line fill.
7.5.1 Bus Errors.
asserted during the entire operation. If the HALT signal is asserted during a
Halt Operation for more information about the halt operation. An alternate
of the operation provided BR is asserted early enough to be internally syn-
chronized before another processor cycle begins. Refer to 7.7 BUS
If the appropriate cache is not enabled or if the cache freeze bit for the cache
is set, the processor does not assert CBREQ. CBREQ is not asserted during
MC68030 recognizes STERM and CBACK and it has asserted CBREQ, it main-
be asserted independently of the CBREQ signal, and burst mode is only
MC68030 executes a full burst operation and fetches four long words, CBREQ
For the purposes of halting the processor or arbitrating the bus away from
burst operation, the processor halts at the end of the operation. Refer to 7.5.3
bus master requesting the bus with BR may become bus master at the end
• CIIN asserted,
• BERR asserted, or
• CBACK negated prematurely.
for more information about bus arbitration.
MC68030 USER'S MANUAL
MOTOROLA
ARBI-