MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 208

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
State 8
State 6
State 7
State 9
State 10
translation descriptor or in a relevant TTx register. Depending on the write
The processor asserts DS during $9 indicating that the data is stable on
the data bus. As long as at least one of the DSACKx signals is recognized
the cycle terminates one clock later. If DSACKx is not recognized by the
times around the end of $8. If wait states are added, the processor con-
tinues to sample DSACKx signals on the falling edges of the clock until
The selected device uses
the appropriate section(s) of the data bus (D24-D31, D16-D23, DS-D15,
The processor asserts ECS and OCS in $6 to indicate that another external
cycle is beginning. The processor drives R/W low for a write cycle. CLOUT
also becomes valid, indicating the state of the MMU CI bit in the address
operation to be performed, the address lines may change during $6.
data buffers during $7. In addition, the ECS (and OCS, if asserted) signal
is negated during $7.
During $8, the processor places the data to be written onto D0-D31.
by the end of $8 (meeting the asynchronous input setup time requirement),
start of $9, the processor inserts wait states instead of proceeding to $10
and $11. To ensure that wait states are inserted, both DSACK0 and DSACK1
must remain negated throughout the asynchronous input setup and hold
one is recognized.
and D0-D7). SIZ0-SIZ1 and A0-A1 select the data bus sections. If it has
stored the data.
The processor issues no new control signals during $10.
In $7, the processor asserts AS, indicating that the address on the address
bus is valid. The processor also asserts DBEN, which can be used to enable
not already done so, the device asserts DSACKx when it has successfully
MC68030 USER'S MANUAL
R/W,
DS, SIZ0-SIZ1, and A0-A1 to latch data from
7-47
7