MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 391

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

10
10-4
10.1.3 Coprocessor Instruction Format
tion with the coprocessor and coordinates any interaction necessary to ex-
to use the functions provided by the coprocessor hardware.
The instruction set of an M68000 coprocessor uses a subset of the F-line
operation words in the M68000 instruction set. The operation word is the
first word of any M68000 Family instruction. The F-line operation word con-
tains ones in bits 15-12 ([15:12]=1111; refer to Figure 10-1); the remaining
additional information necessary for the execution of the coprocessor in-
struction,
As shown in Figure 10-1, bits 9-11 of the F-line operation word encode the
coprocessor identification code (CplD). The MC68030 uses the coprocessor
6-8) contain zeros, the instruction accesses the on-chip memory manage-
type field are unimplemented instructions that cause the MC68030 to begin
cessors and CplD codes of 110-111 are reserved for user-defined coproces-
The instruction set for a given coprocessor is defined by the design of that
coprocessor. When a coprocessor instruction is encountered in the main
processor instruction stream, the MC68030 hardware initiates communica-
ecute the instruction with the coprocessor. A programmer needs to know
only the instruction set and register set defined by the coprocessor in order
bits are coprocessor and instruction dependent. The F-line operation word
may be followed by as many extension words as are required to provide
identification field to indicate the coprocessor to which the instruction ap-
plies. F-line operation words, in which the CplD is zero, are not coprocessor
instructions for the MC68030. If the CplD (bits 9-11) and the type field (bits
ment unit of the MC68030. Instructions with a CplD of zero and a nonzero
exception processing. The MC68030 never generates coprocessor interface
bus cycles with the CplD equal to zero (except via the MOVES instruction).
CplD codes of 001-101 are reserved for current and future Motorola copro-
sors. The Motorola CplD code that is currently defined is 001 for the MC68881
or MC68882 floating-point coprocessor. By default, Motorola assemblers will
use CplD code 001 when generating the instruction operation codes for the
MC68881 or MC68882 coprocessor instructions.
15
14
Figure 10-1. F-Line Coprocessor Instruction Operation Word
13
12
11
MC68030 USER'S MANUAL
0p,0
9
1
8
T PE
6
1
5
T PEOEPEN0 NT
MOTOROLA
0
I