MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 543

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

12
12.5.
12-18
12.5 STATIC RAM MEMORY BANKS
1 A Two-Clock Synchronous Memory Bank Using SRAMs
The MC68030 normally attains its highest performance when the external
tion.
The system must also provide any STERM consolidation circuitry as required
figurations listed above.
When the MC68030 is operating at a high clock frequency, a no-wait-state
following paragraphs discuss three static memory banks, which may be used
as shown or as a starting point for an external cache design. The designs
offer different levels of performance, bus utilization, and cost.
section describes a complete memory bank containing 64K bytes that can
operate with a 20-MHz MC68030 using two-clock accesses. Also discussed
are several options and minor alterations to reduce cost or power consump-
The memory bank can be divided into three sections:
access has one additional clock period, the third access has two additional
clock periods, and the fourth has three additional clock periods. Thus, the
access time for the first cycle determines the critical timing paths.
external memory system will most likely be composed of static RAMs. The
memory system can support a two-clock synchronous bus protocol. This
Figure 12-9 shows the complete memory bank and its connection to the
MC68030. As drawn, the required parts include:
(e.g., by the presence of multiple synchronous memory banks or ports). In
Figure 12-9, this consolidation circuitry is shown as an AND gate.
Memory that is 64 bits wide presents a compromise between the two con-
(8) 16K×4 SRAMs, 35-ns access time with separate I/O pins
(4) 74F244 buffers
(2) 74F32 OR gates
(1) PAL16L8D (or equivalent)
2. The actual memory section (SRAMs), and
3. The buffer section.
1. The byte select and address decode section (provided by the PAL),
MC68030 USER'S MANUAL
MOTOROLA