MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 280

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
traced instruction - - that is, the execution of a traced instruction is not com-
occurs before the interrupt exception processing starts. If an instruction forces
tions for a more complete discussion of exception priorities.
When the processor is inthe trace mode and attempts to execute an illegal
tion emulation routine t h a t performs the instruction function, adjusts the
tion.
The exception processing for a trace starts at the end of normal processing
for the traced instruction and before the start of the next instruction. The
trace exception and saves the trace exception vector offset, program counter
value, and the copy of the status register on the supervisor stack. The saved
value of the program counter is the logical address of the next instruction
to be executed. Instruction execution resumes after the required prefetches
from the address in the trace exception vector.
In general terms, a trace exception is an extension to the function of any
plete until the trace exception processing is completed: If an instruction does
not complete due to a bus error or address error exception, trace exception
processing is deferred until after the execution of the suspended instruction
is resumed and the instruction execution completes normally. If an interrupt
is pending at the completion of an instruction, the trace exception processing
an exception as part of its normal execution, the forced exception processing
occurs before the trace exception is processed. See 8.1.12 Multiple Excep-
or unimplemented instruction, that instruction does not cause a trace ex-
ception since it is not executed. This is of particular importance to an instruc-
stacked program counter to skip the unimplemented instruction, and returns.
checked. If tracing is enabled, the trace exception processing should also be
emulated for the trace exception handler to account for the emulated instruc-
processor makes an internal copy of the status register and enters the su-
pervisor privilege level. It also clears the TO and T1 bits of the status register,
disabling further tracing. The processor supplies vector number 9 for the
Before returning, the trace bits of the status register on the stack should be
T1
0
0
1
1
TO
0
0
1
1
MC68030 USER'S MANUAL
Table 8-3. Tracing Control
Trace on Instruction Execution (Any Instruction)
Trace on Change of Row (BRA, JMP, etc,)
Undefined, Reserved
No Tracing
Tracing Function
8-13
8