MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 399

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

to
10-12
10.2.2 C o p r o c e s s o r C o n d i t i o n a l I n s t r u c t i o n s
the command CIR, the main processor reads the response CIR and responds
the instruction, it provides a response to release the processor. The main
to 10.5,2.5 TRACE EXCEPTIONS).
The coprocessor interface protocol shown in Figure 10-7 allows the copro-
cessor to define the operation of each general category instruction. That is,
the main processor initiates the instruction execution by writing the instruc-
tion command word to the command CIR and by reading the response CIR
to determine its next action. The execution of the coprocessor instruction is
then defined by the internal operation of the coprocessor and by its use of
struction protocol allows a wide range of operations to be implemented in
the general instruction category.
The conditional instruction category provides program control based on the
operations of the coprocessor. The coprocessor evaluates a condition and
completes the execution of the instruction based on this true/false condition
The implementation of instructions in the conditional category promotes
efficient use of both the main processor's and the coprocessor's hardware.
The condition specified for the instruction is related to the coprocessor op-
While the coprocessor is executing an instruction, it requests any required
services from and communicates status to the main processor by placing
coprocessor response primitive codes in the response CIR. After writing to
appropriately. When the coprocessor has completed the execution of an
processor can then execute the next instruction in the instruction stream.
communication with the coprocessor until the coprocessor indicates that it
has completed all processing associated with the cpGEN instruction (refer
response primitives to request services from the main processor. This in-
returns a true/false indicator to the main processor. The main processor
indicator.
eration and is, therefore, evaluated by the coprocessor. The instruction com-
pletion following the condition evaluation is, however, directly related to the
operation of the main processor. The main processor performs the change
of flow, the setting of a byte, or the TRAP operation, since its architecture
explicitly implements these operations for its instruction set.
instruction or no longer needs the services of the main processor to execute
However, if a trace exception is pending, the MC68030 does not terminate
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