MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 180

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment
MOTOROLA
the memory is long-word organized, no further bus cycles are necessary.
The combination of operand size, operand alignment, and port size deter-
for write cycles and noncachable read cycles.
address in long-word-organized memory. In this example, a long-word access
bus cycle then consists of a three-byte access to a long-word boundary. Since
mines the number of bus cycles required to perform a particular memory
access. Table 7-6 shows the number of bus cycles required for different
operand sizes to different port sizes with all possible alignment conditions
This table shows that bus cycle throughput is significantly affected by port
size and alignment. The MC68030 system designer and programmer should
cations.
Figures 7-15 and 7-16 show an example of a long-word transfer to an odd
is attempted beginning at the least significant byte of a long-word-organized
memory. Only one byte can be transferred in the first bus cycle. The second
Figure 7-17 shows the equivalent operation for a cachable data read cycle.
be aware of and account for these effects, particularly in time-critical appli-
Data Port S i z e - 32 Bits:16 Bits:8 Bits
*Instruction prefetches are always two words from a long-word boundary.
!Word Operand
! Long-Word Operand
Instruction*
Byte Operand
Table 7-6. Memory Alignment and Port Size Influence
A1/A0
MC68030 USER'S MANUAL
on Write Bus Cycles
1:2:4
1:1:1
1:1:2
1:2:4
00
Number of Bus Cycles
2:3:4
1:1:1
1:2:2
N/A
01
1:1:1
2:2:4
N/A
1:1:2
10
2:2:2
1:1:1
2:3:4
N/A
11
7-19
7