MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 495

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

11.6.3
11.6.4 Calculate I m m e d i a t e Effective A d d r e s s (ciea)
11-32
The calculate immediate effective address table indicates the number of clock
first level of indirection on memory indirect addressing modes. The effective
coding Summary). For instruction-cache case and for no-cache case, the total
All timing data assumes two-clock reads and writes.
periods needed for the processor to fetch the immediate source operand and
calculate the specified destination effective address, In the case of two-word
instructions, this table indicates the number of clock periods needed for the
processor to fetch the second word of the instruction and calculate the spec-
ified source operand or single operand. Fetch time is only included for the
addresses are divided by their formats (refer to 2.5 Effective Address En-
prefetch, and write cycles is given inside the parentheses as (r/p/w). The read,
I
number of clock cycles is outside the parentheses. The number of read,
prefetch, and write cycles are included in the total clock cycle number.
FULL FORMAT EXENSION WORD(S) (CONTINUED)
NOTE: Xn cannot be in B and I at the same time. Scaling and size of Xn do not affect timing.
• ([d32,B],l,d16)
%= No clock cycles incurred by effective address calculation
Calculate Effective A d d r e s s (cea) ( C o n t i n u e d )
B= Base address: 0. An, PC, Xn, An +Xn, PC+Xn. Form does not affect timing.
([d16,B],d32)
([d16,B],l,d32)
([d32,B])
([d32,B],l)
([d32,B],d16)
([d32,B],d32)
([d32,B],l,d32)
i= Index: 0. Xn
Address Mode
M C 6 8 0 3 0 U S E R ' S M A N U A L
I
Head
4
4
4
4
4
4
4
4
I
0
0
0
0
0
0
0
0
Tail
I I-Cache Case INo-Cache Casel
14(1/0/0)
14(1/0/0)
16(1/0/0)
16(1/0/0)
18(1/0/0)
18(1/0/0)
18(1/0/0)
18(1/0/0)
M O T O R O L A
16(1/2/0)
16(1/2/0)
20(1/2/0)
20(1/2/0)
20(1/3/0)
20(1/3/0)
17(1/2/0)
17(1/2/0)