MC68030RC20C Freescale Semiconductor, MC68030RC20C Datasheet - Page 164

• Manufacturer Part Number: MC68030RC20C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC20C

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.1.1 Bus Control Signals
MOTOROLA
A device with a 32-bit port size can also provide a synchronous mode transfer.
while address strobe (AS) is asserted), regardless of when the signals are
MC68030 E/ectrica/ Specifications).
Synchronous inputs (STERM, CBACK, and ClIN) must remain stable during
a sample window for all rising edges of the clock during a bus cycle (i.e.,
asserted or negated, to ensure proper operation. This sample window is
defined by the synchronous input setup and hold times (see MC68030EC/D,
The external cycle start (ECS) signal is the earliest indication that the pro-
the address, size, function code, read/write, and cache inhibit-out outputs
In synchronous operation, input signals are externally synchronized to the
processor clock, and the synchronizing delay is not incurred.
cessor is initiating a bus cycle. The MC68030 initiates a bus cycle by driving
and by asserting ECS. However, if the processor finds the required program
or data item in an on-chip cache, if a miss occurs in the address translation
cache (ATC) of the memory management unit (MMU), or if the MMU finds
a fault with the access, the processor aborts the cycle before asserting AS.
ECS can be used to initiate various timing sequences that are eventually
qualified with AS. Qualification with AS may be required since, in the case
of an internal cache hit, an ATC miss, or an MMU fault, a bus cycle may be
aborted after ECS has been asserted. The assertion of AS ensures that the
cycle has not been aborted by these internal conditions.
start (OCS) signal is asserted with ECS. When several bus cycles are required
During the first external bus cycle of an operand transfer, the operand cycle
C L K
E X T
Figure 7-2. Asynchronous Input Sample Window
MC68030 USER'S MANUAL
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