ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet
ST72T511R9T6
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ST72T511R9T6 Summary of contents
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MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES Memories – 16K to 60K bytes Program memory (ROM,OTP and EPROM) with read-out protection 2 – 256 bytes E PROM Data memory (only on ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72311R, ST72511R, ST72512R, ST72532R 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI ...
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HALT and ACTIVE-HALT Modes 12.4.4 Supply and Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72311R, ST72511R, ST72512R, ST72532R 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72311R, ST72511R, ST72512R and ST72532R devices are members of the ST7 mi- crocontroller family. They can be grouped as fol- lows: – ST725xxR devices are designed for mid-range applications with ...
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PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout (HS) PE4 1 (HS) PE5 2 (HS) PE6 3 (HS) PE7 4 PWM3 / PB0 ...
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ST72311R, ST72511R, ST72512R, ST72532R PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to Section 12 ”ELECTRICAL CHARACTERISTICS” on page 131. Legend / Abbreviations for Table 1: Type input output supply Input level: A ...
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Pin n Level Pin Name SS_3 25 PF0/MCO I PF1/BEEP I PF2 I PF3/OCMP2_A I PF4/OCMP1_A I PF5/ICAP2_A I ...
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ST72311R, ST72511R, ST72512R, ST72532R Pin n Level Pin Name 61 PE0/TDO I PE1/RDI I PE2/CANTX I PE3/CANRX I/O C Notes the interrupt input column, “eiX” defines the associated external interrupt vector. If ...
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REGISTER & MEMORY MAP As shown in the Figure 3, the MCU is capable of addressing 64K bytes of memories and I/O regis- ters. The available memory locations consist of 128 bytes of register location 2Kbytes of ...
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ST72311R, ST72511R, ST72512R, ST72532R Table 2. Hardware Register Map Register Address Block Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h 0004h PCDR 0005h Port C PCDDR 0006h PCOR 0007h 0008h PBDR 0009h Port B PBDDR 000Ah PBOR 000Bh ...
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Register Address Block Label 002Ah WDGCR WATCHDOG 002Bh WDGSR 002Ch EEPROM EECSR 002Dh to 0030h 0031h TACR2 0032h TACR1 0033h TASR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh TAACLR 003Ch ...
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ST72311R, ST72511R, ST72512R, ST72532R Register Address Block Label 0058h 0059h 005Ah CANISR 005Bh CANICR 005Ch CANCSR 005Dh CANBRPR 005Eh CAN CANBTR 005Fh CANPSR 0060h to 006Fh 0070h ADCDR ADC 0071h ADCCSR 0072h PWMDCR3 0073h PWMDCR2 0074h PWMDCR1 0075h PWMDCR0 PWM ...
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... EPROM PROGRAM MEMORY The program memory of the OTP and EPROM de- vices can be programmed with EPROM program- ming tools available from STMicroelectronics EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo cur- rent ...
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ST72311R, ST72511R, ST72512R, ST72532R 3 DATA EEPROM 3.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. ...
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DATA EEPROM (Cont’d) 3.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 5 describes these different memory access modes. Read Operation ...
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ST72311R, ST72511R, ST72512R, ST72532R DATA EEPROM (Cont’d) 3.4 POWER SAVING MODES Wait mode The DATA EEPROM can enter WAIT mode on ex- ecution of the WFI instruction of the microcontrol- ler. The DATA EEPROM will immediately enter this mode if ...
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DATA EEPROM (Cont’d) 3.6 REGISTER DESCRIPTION CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h Bit 7:3 = Reserved, forced by hardware to 0. Bit Interrupt enable This bit is ...
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ST72311R, ST72511R, ST72512R, ST72532R 4 CENTRAL PROCESSING UNIT 4.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 MAIN FEATURES Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply ...
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CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just ...
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ST72311R, ST72511R, ST72512R, ST72532R CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 SP2 The Stack Pointer is a 16-bit register which is al- ...
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SUPPLY, RESET AND CLOCK MANAGEMENT The ST72311R, ST72511R, ST72512R and ST72532R microcontrollers include a range of util- ity features for securing the application in critical situations (for example in case of a power brown- out), and reducing the number ...
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ST72311R, ST72511R, ST72512R, ST72532R 5.1 LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below a V ...
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RESET SEQUENCE MANAGER (RSM) 5.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure 12: External RESET source pulse Internal LVD RESET (Low Voltage Detection) Internal WATCHDOG RESET These sources act on the RESET ...
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ST72311R, ST72511R, ST72512R, ST72532R RESET SEQUENCE MANAGER (Cont’d) 5.2.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ...
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LOW CONSUMPTION OSCILLATOR The f main clock of the ST7 can be generated OSC by two different source types: an external source a crystal or ceramic resonator oscillators The associated hardware configuration are shown in Table 4. Refer to ...
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ST72311R, ST72511R, ST72512R, ST72532R 6 INTERRUPTS 6.1 INTRODUCTION The ST7 enhanced interrupt management pro- vides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority management: – software programmable nesting ...
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INTERRUPTS (Cont’d) Servicing Pending Interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is deter- mined by the following two-step process: – the highest software priority interrupt is serviced, – if ...
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ST72311R, ST72511R, ST72512R, ST72532R INTERRUPTS (Cont’d) 6.3 INTERRUPTS AND LOW POWER MODES All interrupts allow the processor to exit the WAIT low power mode. On the contrary, only external and other specified interrupts allow the processor to exit the HALT ...
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INTERRUPTS (Cont’d) 6.5 INTERRUPT REGISTER DESCRIPTION CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These two bits indicate the current interrupt ...
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ST72311R, ST72511R, ST72512R, ST72532R INTERRUPTS (Cont’d) Table 6. Dedicated Interrupt Instruction Set Instruction New Description HALT Entering Halt mode IRET Interrupt routine return JRM Jump if I1:0=11 JRNM Jump if I1:0<>11 POP CC Pop CC from the Stack RIM Enable ...
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INTERRUPTS (Cont’d) Table 8. Nested Interrupts Register Map and Reset Values Address Register 7 Label (Hex.) ei1 0024h ISPR0 I1_3 Reset Value 1 SPI 0025h ISPR1 I1_7 Reset Value 1 EEPROM 0026h ISPR2 I1_11 Reset Value 1 0027h ISPR3 Reset ...
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ST72311R, ST72511R, ST72512R, ST72532R 7 POWER SAVING MODES 7.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): SLOW, ...
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POWER SAVING MODES (Cont’d) 7.3 WAIT MODE WAIT mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. All peripherals remain active. During WAIT ...
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ST72311R, ST72511R, ST72512R, ST72532R POWER SAVING MODES (Cont’d) 7.4 ACTIVE-HALT AND HALT MODES ACTIVE-HALT and HALT modes are the two low- est power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruc- tion. The decision ...
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POWER SAVING MODES (Cont’d) 7.4.2 HALT MODE The HALT mode is the lowest power consumption mode of the MCU entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is ...
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ST72311R, ST72511R, ST72512R, ST72532R 8 I/O PORTS 8.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip ...
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I/O PORTS (Cont’d) Figure 25. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION Table 9. I/O ...
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ST72311R, ST72511R, ST72512R, ST72532R I/O PORTS (Cont’d) Table 10. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS R PU PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O PORTS R PU PAD NOT IMPLEMENTED ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST72311R, ST72511R, ST72512R, ST72532R I/O PORTS (Cont’d) 8.4 LOW POWER MODES Mode Description No effect on I/O ports. External interrupts WAIT cause the device to exit from WAIT mode. No effect on I/O ports. External interrupts HALT cause the device ...
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I/O PORTS (Cont’d) 8.5.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read/Write Reset Value: 0000 0000 (00h Bit 7:0 = ...
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ST72311R, ST72511R, ST72512R, ST72532R I/O PORTS (Cont’d) Table 12. I/O Port Register Map and Reset Values Address Register 7 Label (Hex.) Reset Value 0 of all IO port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 0004h PCDR 0005h PCDDR ...
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MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several features such as the external interrupts or the I/Oalternate functions. 9.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the IPA, IPB and ISxx bits of the ...
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ST72311R, ST72511R, ST72512R, ST72532R MISCELLANEOUS REGISTERS (Cont’d) 9.3 MISCELLANEOUS REGISTERS MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS21 IS20 CP1 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using ...
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MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read/Write Reset Value: 0000 0000 (00h) 7 IPA IPB BC1 BC0 TLIS TLIE Bit 7 = IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port ...
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ST72311R, ST72511R, ST72512R, ST72532R MISCELLANEOUS REGISTERS (Cont’d) Table 13. Miscellaneous Register Map and Reset Values Address Register 7 Label (Hex.) MISCR1 IS11 0020h Reset Value 0 MISCR2 IPA 0040h Reset Value 0 48/164 IS10 MCO IS21 ...
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ON-CHIP PERIPHERALS 10.1 WATCHDOG TIMER (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program ...
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ST72311R, ST72511R, ST72512R, ST72532R WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between ...
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WATCHDOG TIMER (Cond’t) Table 15. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah Reset Value 0 WDGSR - 002Bh Reset Value 0 ST72311R, ST72511R, ST72512R, ST72532R ...
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ST72311R, ST72511R, ST72512R, ST72532R 10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler a clock-out signal to supply external devices a real time clock ...
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d) 10.2.4 Register Description MISCELLANEOUS REGISTER 1 (MISCR1) See “MISCELLANEOUS REGISTERS” Section. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read/Write Reset Value: 0000 0001 (01h TB1 TB0 Bit 7:4 ...
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ST72311R, ST72511R, ST72512R, ST72532R 10.3 PWM AUTO-RELOAD TIMER (ART) 10.3.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto reload counter with compare capabilities and of a 7-bit prescaler clock source. These resources allow three ...
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PWM AUTO-RELOAD TIMER (Cont’d) 10.3.2 Functional Description Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every ris- ing edge of the clock signal possible to read or write ...
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ST72311R, ST72511R, ST72512R, ST72532R PWM AUTO-RELOAD TIMER (Cont’d) Independent PWM signal generation This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins with minimum core processing overhead. This function is stopped ...
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PWM AUTO-RELOAD TIMER (Cont’d) Output compare and Time base interrupt On overflow, the OVF flag of the CSR register is set and an overflow interrupt request is generated if the overflow interrupt enable bit, OIE, in the CSR register, is ...
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ST72311R, ST72511R, ST72512R, ST72532R PWM AUTO-RELOAD TIMER (Cont’d) 10.3.3 Register Description CONTROL / STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 EXCL CC2 CC1 CC0 TCE FCRL Bit 7 = EXCL External Clock This bit is set and ...
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PWM AUTO-RELOAD TIMER (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) 7 OE3 OE2 OE1 OE0 OP3 OP2 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable ...
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ST72311R, ST72511R, ST72512R, ST72532R PWM AUTO-RELOAD TIMER (Cont’d) Table 17. PWM Auto-Reload Timer Register Map and Reset Values Address Register 7 Label (Hex.) PWMDCR3 DC7 0072h 0 Reset Value PWMDCR2 DC7 0073h 0 Reset Value PWMDCR1 DC7 0074h 0 Reset ...
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TIMER 10.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input sig- nals ( input ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) Figure 35. Timer Block Diagram f CPU 8 high 8-bit buffer EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 OCF2 (Status Register) ...
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TIMER (Cont’d) 16-bit read sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read LS Byte Byte is buffered Other instructions Returns the buffered Read ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) Figure 36. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 37. Counter Timing Diagram, internal clock divided by 4 CPU ...
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TIMER (Cont’d) 10.4.3.3 Input Capture In this section, the index may because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) Figure 39. Input Capture Block Diagram ICAP1 pin EDGE DETECT EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 40. Input Capture Timing Diagram TIMER CLOCK FF01 COUNTER REGISTER ...
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TIMER (Cont’d) 10.4.3.4 Output Compare In this section, the index may because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the reg- ister, the output compare function is inhibited until the register is also written the OC ...
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TIMER (Cont’d) Figure 42. Output Compare Timing Diagram, f INTERNAL CPU CLOCK TIMER CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCR i ) OUTPUT COMPARE FLAG i (OCF i ) OCMP i PIN (OLVL i =1) Figure 43. Output ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) 10.4.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse ...
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TIMER (Cont’d) Figure 44. One Pulse Mode Timing Example FFFC FFFD FFFE COUNTER ICAP1 OCMP1 Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 Figure 45. Pulse Width Modulation Mode Timing Example FFFC FFFD FFFE COUNTER 34E2 OCMP1 compare2 Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) 10.4.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The ...
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TIMER (Cont’d) 10.4.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from WAIT mode. 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) 10.4.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag 1. 0: ...
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TIMER (Cont’d) OUTPUT COMPARE 2 HIGH (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 LOW ...
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ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER (Cont’d) Table 19. 16-Bit Timer Register Map and Reset Values Address Register 7 Label (Hex.) Timer A: 32 CR1 ICIE Timer B: 42 Reset Value 0 Timer A: 31 CR2 OC1E Timer B: 41 ...
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SERIAL PERIPHERAL INTERFACE (SPI) 10.5.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 47. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS 80/164 Internal Bus DR SPIF WCOL SPI STATE CONTROL SPIE SPE SPR2 MSTR MASTER ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4 Functional Description Figure 46 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a sequence of eight ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 49. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit Bit 6 MISO (from master) MSBit Bit 6 MOSI (from slave) SS (to slave) CAPTURE ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- pens, the transfer ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an MCU as the ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from WAIT mode. SPI registers are frozen. HALT In HALT mode, the SPI is ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 10.5.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. 0: Interrupt ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF - Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 21. SPI Register Map and Reset Values Address Register 7 Label (Hex.) SPIDR MSB 0021h Reset Value x SPICR SPIE 0022h Reset Value 0 SPISR SPIF 0023h Reset Value 0 ST72311R, ST72511R, ST72512R, ST72532R 6 ...
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ST72311R, ST72511R, ST72512R, ST72532R 10.6 SERIAL COMMUNICATIONS INTERFACE (SCI) 10.6.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 52. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE ILIE SCI INTERRUPT CONTROL TRANSMIT TER CLOCK f CPU /2 /16 ST72311R, ST72511R, ST72512R, ST72532R ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 52. It contains 6 dedicated reg- isters: – Two control registers (CR1 & CR2) – A status ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram EXTE NDED PRESCALER TRANSMITTE R RATE CONTROL EXTE NDED TRANS MITTER PRESCALE R REGISTER EXTE NDED RECEIVER PRESCALER REGISTER EXTE NDED PRESCALER RECEIVER RATE CONTROL f ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.4.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows CPU (32 (32 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving until Halt mode ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d) 10.6.7 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR NF Bit 7 = TDRE Transmit data register empty. This bit is set ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAK E - Bit Receive data bit 8. This bit is used to store the 9th bit of the received ...
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ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ERPR ...
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ST72311R, ST72511R, ST72512R, ST72532R 10.7 CONTROLLER AREA NETWORK (CAN) 10.7.1 Introduction This peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in CAN specification Rev. 2.0 part A. It can also be ...
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CONTROLLER AREA NETWORK (Cont’d) 10.7.2 Main Features – Support of CAN specification 2.0A and 2.0B pas- sive – Three prioritized 10-byte Transmit/Receive mes- sage buffers – Two programmable global 12-bit message ac- ceptance filters – Programmable baud rates up to ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) Figure 56. CAN Frames Inter-Frame Space Arbitration Field 12 ID Inter-Frame Space Arbitration Field 12 ID Data Frame or Remote Frame Error Frame Flag Echo Error Flag 6 6 Any Frame Inter-Frame ...
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CONTROLLER AREA NETWORK (Cont’d) 10.7.3.3 Modes of Operation The CAN Core unit assumes one of the seven states described below: – STANDBY. Standby mode is entered either on a chip reset or on resetting the RUN bit in the Con- ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) – RESYNC. The resynchronization mode is used to find the correct entry point for starting trans- mission or reception after the node has gone asynchronous either by going into the STANDBY or ...
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CONTROLLER AREA NETWORK (Cont’d) – ERROR. The error management as described in the CAN protocol is completely handled by hard- ware using 2 error counters which get increment decremented according to the error condition. Both of them may ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) 10.7.3.4 Bit Timing Logic The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and re- synchronizing on following ...
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CONTROLLER AREA NETWORK (Cont’d) 10.7.4 Register Description The CAN registers are organized as 6 general pur- pose registers plus 5 pages of 16 registers span- ning the same address space and primarily used for message and filter storage. The page ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) INTERRUPT CONTROL REGISTER (ICR) Read/Write Reset Value: 00h 7 0 ESCI RXIE TXIE SCIE ORIE Bit 6 = ESCI Extended Status Change Interrupt Read/Set/Clear Set by software to specify that SCIF is ...
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CONTROLLER AREA NETWORK (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 00h 7 0 BOFF EPSV SRTE NRTX FSYN WKPS Bit 6 = BOFF Bus-Off State Read Only Set by hardware to indicate that the node is in bus- off state, ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) BAUD RATE PRESCALER REGISTER (BRPR) Read/Write in Standby mode Reset Value: 00h 7 RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 RJW[1:0] determine the maximum number of time quanta by which a bit ...
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CONTROLLER AREA NETWORK (Cont’d) 10.7.4.2 Paged Registers LAST IDENTIFIER HIGH REGISTER (LIDHR) Read/Write Reset Value: Undefined 7 LID10 LID9 LID8 LID7 LID6 LID5 LID[10:3] are the most significant 8 bits of the last Identifier read on the CAN bus. LAST ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) IDENTIFIER LOW REGISTERS (IDLRx) Read/Write Reset Value: Undefined 7 ID2 ID1 ID0 RTR DLC3 DLC2 ID[2:0] are the least significant 3 bits of the 11-bit message identifier. RTR is the Remote Transmission ...
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CONTROLLER AREA NETWORK (Cont’d) FILTER HIGH REGISTERS (FHRx) Read/Write Reset Value: Undefined 7 FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FIL[11:3] are the most significant 8 bits of a 12-bit message filter. The acceptance filter is compared bit by bit with ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) Figure 60. CAN Register Map 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 6Fh 118/164 Interrupt Status Interrupt Control Control/Status Baud Rate Prescaler Bit Timing Page Selection Paged Reg1 Paged Reg1 Paged Reg0 ...
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CONTROLLER AREA NETWORK (Cont’d) Figure 61. Page Maps PAGE 0 PAGE 1 LIDHR IDHR1 60 h LIDLR IDLR1 61 h DATA DATA DATA DATA DATA ...
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ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) Table 23. CAN Register Map and Reset Values Address Register Page (Hex.) Label CANISR 5A Reset Value CANICR 5B Reset Value CANCSR 5C Reset Value CANBRPR 5D Reset Value CANBTR 5E Reset ...
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A/D CONVERTER (ADC) 10.8.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer ...
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ST72311R, ST72511R, ST72512R, ST72532R 8-BIT A/D CONVERTER (ADC) (Cont’d) 10.8.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. ...
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A/D CONVERTER (ADC) (Cont’d) 10.8.6 Register Description CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 CH2 Bit 7 = COCO Conversion Complete This bit is set by hardware cleared by ...
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ST72311R, ST72511R, ST72512R, ST72532R 8-BIT A/D CONVERTOR (ADC) (Cont’d) Table 24. ADC Register Map and Reset Values Address Register 7 Label (Hex.) ADCDR D7 0070h Reset Value 0 ADCCSR COCO 0071h Standard 0 Reset Value 124/164 ...
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INSTRUCTION SET 11.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) ...
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ST72311R, ST72511R, ST72512R, ST72532R INSTRUCTION SET OVERVIEW (Cont’d) 11.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction Function NOP No operation ...
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INSTRUCTION SET OVERVIEW (Cont’d) 11.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of an index register ...
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ST72311R, ST72511R, ST72512R, ST72532R INSTRUCTION SET OVERVIEW (Cont’d) 11.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional ...
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INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Function /Example ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory tst ...
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ST72311R, ST72511R, ST72512R, ST72532R INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Function /Example JRULE Jump Unsigned <= LD Load dst <= src MUL Multiply X NEG Negate (2’s compl) neg $10 ...
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ELECTRICAL CHARACTERISTICS 12.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 12.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst condi- tions of ...
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ST72311R, ST72511R, ST72512R, ST72532R 12.2 ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- ...
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OPERATING CONDITIONS 12.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f External clock frequency OSC T Ambient temperature range A Figure 66. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 FUNCTIONALI TY NOT GUARANTEED ...
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ST72311R, ST72511R, ST72512R, ST72532R OPERATING CONDITIONS (Cont’d) 12.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating condition for V Symbol Parameter Reset release threshold V IT+ (V rise) DD Reset generation threshold V IT- (V fall) DD ...
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SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- Symbol Parameter I Supply current variation ...
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ST72311R, ST72511R, ST72512R, ST72532R SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.2 WAIT and SLOW WAIT Modes Symbol Parameter 3) Supply current in WAIT mode (see Figure 71) Supply current in SLOW WAIT mode (see Figure 72 Supply current in ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 12.4.3 HALT and ACTIVE-HALT Modes Symbol Parameter Supply current in HALT mode I DD Supply current in ACTIVE-HALT mode 12.4.4 Supply and Clock Managers The previous current consumption specified for the ST7 functional operating modes over ...
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ST72311R, ST72511R, ST72512R, ST72532R 12.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating condition for V 12.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) 2) Interrupt reaction time t v(IT v(IT) c(INST) 12.5.2 ...
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MEMORY CHARACTERISTICS Subject to general operating condition for V 12.6.1 RAM and Hardware Registers Symbol Parameter 1) V Data retention mode RM 12.6.2 EEPROM Data Memory Symbol Parameter Programming time t prog (for bytes at ...
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ST72311R, ST72511R, ST72512R, ST72532R 12.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 12.7.1 Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), ...
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EMC CHARACTERISTICS (Cont’d) 12.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer ...
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... GENERATOR Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger. ...
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EMC CHARACTERISTICS (Cont’d) 12.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electro- Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit el- ements. The stress generally affects the circuit el- ements ...
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ST72311R, ST72511R, ST72512R, ST72532R EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and ...
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I/O PORT PIN CHARACTERISTICS 12.8.1 General Characteristics Subject to general operating condition for V Symbol Parameter 2) V Input low level voltage Input high level voltage IH V Schmitt trigger voltage hysteresis hys I Input leakage ...
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ST72311R, ST72511R, ST72512R, ST72532R I/O PORT PIN CHARACTERISTICS (Cont’d) 12.8.2 Output Driving Current Subject to general operating condition for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see ...
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CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating condition for V Symbol Parameter 2) V Input low level voltage Input high level voltage IH V Schmitt trigger voltage hysteresis hys R Weak pull-up ...
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ST72311R, ST72511R, ST72512R, ST72532R 12.10 TIMER PERIPHERAL CHARACTERISTICS Subject to general operating condition for V , and T unless otherwise specified 12.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 12.10.2 8-Bit PWM-ART Auto-Reload Timer Symbol Parameter ...
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COMMUNICATIONS INTERFACE CHARACTERISTICS 12.11.1 SPI - Serial Peripheral Interface Subject to general operating condition for V , and T unless otherwise specified Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise and ...
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ST72311R, ST72511R, ST72512R, ST72532R COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d) Figure 89. SPI Slave Timing Diagram with CPHA=1 SS INPUT t su(SS) CPHA=0 CPOL=0 CPHA=0 CPOL w(SCKH) a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI MSB ...
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COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d) 12.11.2 SCI - Serial Communications Interface Subject to general operating condition for V , and T unless otherwise specified Symbol Parameter f Tx Communication frequency 8MHz f Rx 12.11.3 CAN - Controller Area Network ...
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ST72311R, ST72511R, ST72512R, ST72532R 12.12 8-BIT ADC CHARACTERISTICS Subject to general operating condition for V Symbol Parameter f ADC clock frequency ADC 2) V Conversion range voltage AIN R External input resistor AIN R Internal input resistor ADC C Internal ...
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ADC CHARACTERISTICS (Cont’d) ADC Accuracy with V =5.0V DD Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity ...
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ST72311R, ST72511R, ST72512R, ST72532R 13 PACKAGE CHARACTERISTICS 13.1 PACKAGE MECHANICAL DATA Figure 93. 64-Pin Thin Quad Flat Package L1 Figure 94. 64-Pin Epoxy Thin Quad Flat Package Note: “ QUALIFICATION OR VOLUME PRODUCTION OF DEVICES USING EPOXY PACKAGES (ESO/EDIL/EQFP) IS ...
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THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D T Maximum junction temperature Jmax Notes: 1. The power dissipation is obtained from the formula P and P is the port power dissipation determined ...
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ST72311R, ST72511R, ST72512R, ST72532R 13.3 SOLDERING AND GLUEABILITY INFORMATION Recommended soldering information given only as design guidelines. Figure 95. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) 250 200 150 80 C Temp 100 PREHEATING PHASE ...
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PACKAGE/SOCKET FOOTPRINT PROPOSAL To solder the TQFP64 device directly on the appli- cation board solder a socket for connecting the emulator probe, the application board should provide the footprint described in Figure 97. This footprint allows both ...
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ST72311R, ST72511R, ST72512R, ST72532R 14 DEVICE CONFIGURATION AND ORDERING INFORMATION Each device is available for production in user pro- grammable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content ...
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... DEVICE PACKAGE RANGE X ST72311R, ST72511R, ST72512R, ST72532R The selected options are communicated to STMicroelectronics using the correctly completed OPTION LIST appended. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. XXX Code name (defined by STMicroelectronics) = LVD disabled S= LVD enabled ...
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... Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phone Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STMicroelectronics references Device ST72311R9 [ ] ST72311R7 [ ] ST72311R6 Package TQFP64 Temperature Range: ...
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... Supported Products ST72311R6, ST72311R7, ST72311R9 ST72511R6, ST72511R7, ST72511R9 ST72512R4 ST72532R4 ST72311R, ST72511R, ST72512R, ST72532R the ST7 from third party manufacturers can be ob- tain from the STMicroelectronics Internet site http//st7.st.com. HIWARE ISYSTEM KANDA LEAP Tools from these manufacturers include C compli- ers, emulators and gang programmers. ...
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... PRODUCT EVALUATION AN910 ST7 and st9 performance benchmarking AN990 ST7 benefits versus industry standard APPLICATIONS EXAMPLES AN1086 ST7 / ST10U435 CAN-Do solutions for car multiplexing TO GET MORE INFORMATION To get the updated information on that product please refer to STMicroelectronics web server. http://st7.st.com/ 162/164 Description ...
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SUMMARY OF CHANGES Description of the changes between the current release of the specification and the previous one. Revision - Section 8.4 ”LOW POWER MODES” on page 42 and Section 8.5 ”INTERRUPTS” on page 42 added in Section 8 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...