ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 47

• Manufacturer Part Number: ST72T511R9T6
• Description: Microcontrollers (MCU) UV EPROM 60K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T511R9T6

• Data Bus Width: 8 bit
• Program Memory Type: EEPROM
• Program Memory Size: 60 KB
• Data Ram Size: 2048 B
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = IPA Interrupt polarity for port A
This bit is used to invert the sensitivity of the port A
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSI-
TIVITY” on page 45 and the description of the IS2x
bits of the MISCR1 register for more details.
Bit 6 = IPB Interrupt polarity for port B
This bit is used to invert the sensitivity of the port B
[3:0] external interrupts. It is set and cleared by
software.
0: No sensitivity inversion
1: Sensitivity inversion
See Section 9.1 ”I/O PORT INTERRUPT SENSI-
TIVITY” on page 45 and the description of the IS1x
bits of the MISCR1 register for more details.
Bit 5:4 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.
IPA
BC1
7
0
0
1
1
IPB
BC0
0
1
0
1
BC1
BC0
Beep mode with f
~500-Hz
~1-KHz
~2-KHz
TLIS
Off
TLIE
~50% duty cycle
OSC
Beep signal
SSM
Output
=16MHz
SSI
0
ST72311R, ST72511R, ST72512R, ST72532R
Bit 3 = TLIS TLI sensitivity
This bit allows to toggle the TLI edge sensitivity. It
can be set and cleared by software only when
TLIE bit is cleared.
0: Falling edge
1: Rising edge
Bit 2 = TLIE TLI enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Note: a parasitic interrupt can be generated when
clearing the TLIE bit.
Bit 1 = SSM SS mode selection
This bit is set and cleared by software.
0: Normal mode - the level of the SPI SS signal is
1: I/O mode (PC7), the level of the SPI SS signal is
Bit 0 = SSI SS internal mode
This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.
input from the external SS pin.
read from the SSI bit.
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