ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 37

• Manufacturer Part Number: ST72T511R9T6
• Description: Microcontrollers (MCU) UV EPROM 60K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T511R9T6

• Data Bus Width: 8 bit
• Program Memory Type: EEPROM
• Program Memory Size: 60 KB
• Data Ram Size: 2048 B
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

POWER SAVING MODES (Cont’d)
7.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 10.2 on page 52 for more de-
tails on the MCCSR register).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 7, “Interrupt
Mapping,” on page 32) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 24).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 14.1 on page 158 for more details).
Figure 23. HALT Timing Overview
[MCCSR.OIE=0]
INSTRUCTION
RUN
HALT
HALT
4096 CPU CYCLE
INTERRUPT
RESET
DELAY
OR
VECTOR
FETCH
RUN
ST72311R, ST72511R, ST72512R, ST72532R
Figure 24. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 7, “Interrupt Mapping,” on page 32 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
N
HALT INSTRUCTION
WATCHDOG
WDGHALT
(MCCSR.OIE=0)
RESET
1
INTERRUPT
Y
1)
ENABLE
3)
4096 CPU CLOCK CYCLE
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
I[1:0] BITS
I[1:0] BITS
N
DELAY
RESET
Y
WATCHDOG
DISABLE
2)
XX
XX
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
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4)
4)