ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 123

Microcontrollers (MCU) UV EPROM 60K SPI/SCI

ST72T511R9T6

Manufacturer Part Number
ST72T511R9T6
Description
Microcontrollers (MCU) UV EPROM 60K SPI/SCI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72T511R9T6

Data Bus Width
8 bit
Program Memory Type
EEPROM
Program Memory Size
60 KB
Data Ram Size
2048 B
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
5
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-64
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
No

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0
8-BIT A/D CONVERTER (ADC) (Cont’d)
10.8.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = COCO Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bit 6 = Reserved. must always be cleared.
Bit 5 = ADON A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved. must always be cleared.
Bit 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*Note: The number of pins AND the channel selec-
tion varies according to the device. Refer to the de-
vice pinout.
COCO
7
Channel Pin*
0
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
ADON
0
CH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CH3
CH2
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CH1
CH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CH0
CH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
ST72311R, ST72511R, ST72512R, ST72532R
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
D7
7
D6
D5
D4
D3
D2
D1
123/164
D0
0

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