ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 34

• Manufacturer Part Number: ST72T511R9T6
• Description: Microcontrollers (MCU) UV EPROM 60K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T511R9T6

• Data Bus Width: 8 bit
• Program Memory Type: EEPROM
• Program Memory Size: 60 KB
• Data Ram Size: 2048 B
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST72311R, ST72511R, ST72512R, ST72532R
7 POWER SAVING MODES
7.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 18): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.
Figure 18. Power Saving Mode Transitions
34/164
ACTIVE HALT
SLOW WAIT
POWER CONSUMPTION
SLOW
HALT
WAIT
RUN
Low
High
CPU
).
7.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
– To adapt the internal clock frequency (f
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f
In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.
Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.
Figure 19. SLOW Mode Clock Transitions
internal clock in the device,
the available supply voltage.
CP1:0
f
f
SMS
OSC
CPU
/2
FREQU ENCY
00
f
NEW SLOW
OSC
REQUEST
/4
01
CPU
f
OSC
NORMAL RUN MODE
).
/8
REQUEST
CPU
f
OSC
) to
/2