ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 30

• Manufacturer Part Number: ST72T511R9T6
• Description: Microcontrollers (MCU) UV EPROM 60K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T511R9T6

• Data Bus Width: 8 bit
• Program Memory Type: EEPROM
• Program Memory Size: 60 KB
• Data Ram Size: 2048 B
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST72311R, ST72511R, ST72512R, ST72532R
INTERRUPTS (Cont’d)
6.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit the HALT modes (see column “Exit from
HALT” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting HALT
mode, the first one serviced can only be an inter-
rupt with exit from HALT mode capability and it is
selected through the same decision process
shown in Figure 15
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
Figure 16. Concurrent interrupt management
Figure 17. Nested interrupt management
30/164
11 / 10
11 / 10
MAIN
MAIN
RIM
RIM
IT2
IT2
IT1
IT1
IT4
TLI
TLI
IT1
IT4
IT0
IT0
6.4 CONCURRENT & NESTED MANAGEMENT
The following Figure 16 and Figure 17 show two
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 17 The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
IT3
IT3
IT1
IT4
IT2
10
10
SOFTWARE
PRIORITY
LEVEL
SOFTWARE
PRIORITY
LEVEL
MAIN
MAIN
3
3
3
3
3
3
3/0
3
3
2
1
3
3
3/0
I1
I1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 0
0 1
1 1
1 1
I0
I0