ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 113

• Manufacturer Part Number: ST72T511R9T6
• Description: Microcontrollers (MCU) UV EPROM 60K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T511R9T6

• Data Bus Width: 8 bit
• Program Memory Type: EEPROM
• Program Memory Size: 60 KB
• Data Ram Size: 2048 B
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

CONTROLLER AREA NETWORK (Cont’d)
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 00h
Bit 6 = BOFF Bus-Off State
Set by hardware to indicate that the node is in bus-
off state, i.e. the Transmit Error Counter exceeds
255.
Reset by hardware to indicate that the node is in-
volved in bus activities.
Bit 5 = EPSV Error Passive State
Set by hardware to indicate that the node is error
passive.
Reset by hardware to indicate that the node is either
error active (BOFF = 0) or bus-off.
Bit 4 = SRTE Simultaneous Receive/Transmit En-
able
Set by software to enable simultaneous transmis-
sion and reception of a message passing the ac-
ceptance filtering. Allows to check the integrity of
the communication path.
Reset by software to discard all messages trans-
mitted by the node. Allows remote and data frames
to share the same identifier.
Read Only
Read Only
7
0
BOFF
Read/Set/Clear
EPSV SRTE NRTX FSYN WKPS
RUN
0
ST72311R, ST72511R, ST72512R, ST72532R
Bit 3 = NRTX No Retransmission
Set by software to disable the retransmission of un-
successful messages.
Cleared by software to enable retransmission of
messages until success is met.
Bit 2 = FSYN Fast Synchronization
Set by software to enable a fast resynchronization
when leaving standby mode, i.e. wait for only 11 re-
cessive bits in a row.
Cleared by software to enable the standard resyn-
chronization when leaving standby mode, i.e. wait
for 128 sequences of 11 recessive bits.
Bit 1 = WKPS Wake-up Pulse
Set by software to generate a dominant pulse when
leaving standby mode.
Cleared by software for no dominant wake-up
pulse.
Bit 0 = RUN CAN Enable
Set by software to leave standby mode after 128 se-
quences of 11 recessive bits or just 11 recessive
bits if FSYN is set.
Cleared by software to request a switch to the
standby or low-power mode as soon as any on-go-
ing transfer is complete. Read-back as 1 in the
meantime to enable proper signalling of the standby
state. The CPU clock may therefore be safely
switched OFF whenever RUN is read as 0.
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
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