ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 45

Microcontrollers (MCU) UV EPROM 60K SPI/SCI

ST72T511R9T6

Manufacturer Part Number
ST72T511R9T6
Description
Microcontrollers (MCU) UV EPROM 60K SPI/SCI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72T511R9T6

Data Bus Width
8 bit
Program Memory Type
EEPROM
Program Memory Size
60 KB
Data Ram Size
2048 B
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
5
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-64
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
No

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9 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over
several features such as the external interrupts or
the I/Oalternate functions.
9.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the Miscellaneous
registers (Figure 27). This control allows to have
up to 4 fully independent external interrupt source
sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
To guarantee correct functionality, the sensitivity
bits in the MISCR registers must be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). See I/O port register and Miscel-
laneous register descriptions for more details on
the programming.
Figure 27. External Interrupt Sources vs MISCR
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
SOURCES
SOURCES
SOURCES
SOURCES
PA3
PA2
PA1
PA0
PB3
PB2
PB1
PB0
PB7
PB6
PB5
PB4
PF2
PF1
PF0
MISCR2.IPA
MISCR2.IPB
ST72311R, ST72511R, ST72512R, ST72532R
9.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers allow to manage four I/O port
miscellaneous alternate functions:
These functions are described in details in the
Section 9.3 ”MISCELLANEOUS REGISTERS” on
page 46.
Main clock signal (f
A Beep signal output on PF1 (with three
selectable audio frequencies)
A TLI management on a dedicated pin
A SPI SS pin internal control to use the PC7 I/O
port function while the SPI is active.
INTERRUPT
INTERRUPT
INTERRUPT
INTER RUPT
SOURCE
SOURCE
SOURCE
SOURCE
ei1
ei2
ei3
ei0
OSC
/2) output on PF0
SENSI TIVITY
SENSI TIVITY
IS20
IS10
CONTROL
CONTROL
MISCR1
MISCR1
IS21
IS11
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