ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 109

Microcontrollers (MCU) UV EPROM 60K SPI/SCI

ST72T511R9T6

Manufacturer Part Number
ST72T511R9T6
Description
Microcontrollers (MCU) UV EPROM 60K SPI/SCI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72T511R9T6

Data Bus Width
8 bit
Program Memory Type
EEPROM
Program Memory Size
60 KB
Data Ram Size
2048 B
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
5
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TQFP-64
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
No

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CONTROLLER AREA NETWORK (Cont’d)
– ERROR. The error management as described in
Figure 58. CAN Error State Diagram
the CAN protocol is completely handled by hard-
ware using 2 error counters which get increment-
ed or decremented according to the error
condition. Both of them may be read by the appli-
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
ERROR ACTI VE
When TECR or RECR > 127, the EPSV bit gets set
the EPSV bit gets cleared
When TECR and RECR < 128,
BUS OFF
ST72311R, ST72511R, ST72512R, ST72532R
cation to determine the stability of the network.
Moreover, as one of the node status bits (EPSV
or BOFF of the CSR register) changes, an inter-
rupt is generated if the SCIE bit is set in the ICR
Register. Refer to Figure 58.
ERROR PASSI VE
When TECR > 255 the BOFF bit gets set
and the EPSV bit gets cleared
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