ST72T511R9T6 STMicroelectronics, ST72T511R9T6 Datasheet - Page 56

• Manufacturer Part Number: ST72T511R9T6
• Description: Microcontrollers (MCU) UV EPROM 60K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T511R9T6

• Data Bus Width: 8 bit
• Program Memory Type: EEPROM
• Program Memory Size: 60 KB
• Data Ram Size: 2048 B
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 5
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-64
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST72311R, ST72511R, ST72512R, ST72532R
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARR register value.
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
Figure 32. PWM Auto-reload Timer Function
Figure 33. PWM Signal from 0% to 100% Duty Cycle
56/164
AUTO-RELOAD
DUTY CYCLE
WITH OEx=1
AND OPx=0
REGISTER
REGISTER
WITH OEx=1
AND OPx=1
(DCRx)
f
(ARR)
PWM
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
COUNTER
f
COUNTER
= f
255
000
COUNTER
FDh
/ (256 - ARR)
FEh
ARR=FDh
FFh
FDh
OPx (output polarity) bit in the PWMCR register.
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARR register.
The maximum available resolution for the PWMx
duty cycle is:
Note: To get the maximum resolution (1/256), the
ARR register must be 0. With this maximum reso-
lution, 0% and 100% can be obtained by changing
the polarity.
FEh
Resolution = 1 / (256 - ARR)
FFh
FDh
FEh
t
t